Xilinx ML410 User Manual page 90

Chapter 2: ML410 Embedded Development Platform
Table 2-48: PM1 Pinout (Cont'd)
FPGA
PM1 Pin
Pin (U37)
C8 AG8
C9 AF15
C10 AG15
C11 AB5
C12 AC5
C13 A7
C14 A6
C15 AC1
C16 AD1
C17 R1
C18 T1
C19 AP9
C20 AP10
D1 AC12
D2 AB12
D3 AE14
D4 AF14
D5 Y7
D6 Y8
D7 AA4
D8 AA5
D9 W4
D10 W5
D11 AH15
D12 AJ15
D13 D1
D14 C1
D15 AJ1
D16 AH1
D17 AA1
D18 Y1
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ML410 Schematic
Pin Description
IO_L27P_12 PM_IO_3V_5
IO_L17P_8 PM_IO_80
IO_L17N_8 PM_IO_81
IO_L7N_12 PM_IO_3V_19
IO_L7P_12 PM_IO_3V_24
RXPPADA_113 RXPPADA_113
RXNPADA_113 RXNPADA_113
RXPPADA_110 RXPPADA_110
RXNPADA_110 RXNPADA_110
TXPPADA_112 TXPPADA_112
TXNPADA_112 TXNPADA_112
TXPPADA_109 TXPPADA_109
TXNPADA_109 TXNPADA_109
IO_L5P_8 PM_IO_92
IO_L5N_8 PM_IO_93
IO_L13P_8 PM_IO_84
IO_L13N_8 PM_IO_85
IO_L5N_12 PM_IO_3V_21
IO_L5P_12 PM_IO_3V_20
IO_L3N_12 PM_IO_3V_8
IO_L3P_12 PM_IO_3V_6
IO_L1N_12 PM_IO_3V_2
IO_L1P_12 PM_IO_3V_14
IO_L21P_8 PM_IO_78
IO_L21N_8 PM_IO_79
TXNPADB_113 TXNPADB_113
TXPPADB_113 TXPPADB_113
TXNPADB_110 TXNPADB_110
TXPPADB_110 TXPPADB_110
RXNPADB_112 RXNPADB_112
RXPPADB_112 RXPPADB_112
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FPGA Bank
Net V
CCO
3V Single-ended 50Ω impedance
2.5V LVDS pair 100Ω differential
impedance; can also be used as
2.5V
single-ended
3V Single-ended 50Ω impedance
3V Single-ended 50Ω impedance
MGT RX pair received by host
FPGA
MGT RX pair received by host
FPGA
MGT TX pair driven by host
FPGA
MGT TX pair driven by host
FPGA
2.5V Single-ended 50Ω impedance
2.5V Single-ended 50Ω impedance
2.5V Single-ended 50Ω impedance
2.5V Single-ended 50Ω impedance
3V Single-ended 50Ω impedance
3V Single-ended 50Ω impedance
3V Single-ended 50Ω impedance
3V Single-ended 50Ω impedance
3V Single-ended 50Ω impedance
3V Single-ended 50Ω impedance
2.5V LVDS pair 100Ω differential
impedance; can also be used as
2.5V
single-ended
MGT TX pair driven by host
FPGA
MGT TX pair driven by host
FPGA
MGT RX pair received by host
FPGA
ML410 Embedded Development Platform
Pin Function
UG085 (v1.7.2) December 11, 2008
R