Ddr Sdram Sodimm Memory - Xilinx Virtex-4 ML455 User Manual

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DDR SDRAM SODIMM Memory

The ML455 board contains a 200-pin, small-outline dual in-line memory module
(SODIMM) connector (J4) that supports installation of DDR SDRAM SODIMM memory
modules of 128 MB, 256 MB, 512 MB, or 1 GB. Xilinx provides a 128 MB memory SODIMM
Micron Semiconductor part number MT8VDDT1664HDG-265B3, with the kit.
provides a description of the memory interface signal descriptions, SODIMM connector
pin assignments, and associated FPGA pin assignments.
The ML455 board does not support a 72-bit DDR data interface required for parity or error
correction codes (ECC).
Characteristics of the DDR SDRAM SODIMM (provided with the kit):
•
•
•
•
The data sheet for the DDR SDRAM Small Outline DIMM memory module kit can be
obtained from Micron Semiconductor at www.micron.com/products/modules. Contact
Micron for availability of other compatible products, including device capacity, clock
speeds, and CAS latency options, in the 200-pin SODIMM form factor.
The ML455 board memory interface design includes on board 50 Ω termination resistors to
V
data-bus and the 8 bit bidirectional DQS signals. The address and control signals have 50 Ω
termination resistors to V
120 Ω termination network for the differential clock inputs. The Xilinx Digitally Controlled
Impedance (DCI) standard SSTL2_I_DCI can be utilized to terminate unidirectional
address and control signals transmitted by the FPGA. External 50 Ω reference resistors are
provided to VRN and VRP for the memory interface banks 7 and 8 of the XC4VLX25
FPGA. See the Virtex-4 User Guide for additional information on DCI.
Table 3-2: SDRAM Memory Interface Signal Descriptions
www.BDTIC.com/XILINX
14
Organization 16M x 64 bit
Memory clock speed 7.5 ns/133 MHz
CAS latency 2.5
2.5V I/O (Stub-Series Terminated Logic (SSTL2) compatible)
, at both the FPGA and SODIMM ends of the interface, for the 64 bit bidirectional DQ
TT
TT
SODIMM
Signal
J4 Pin #
112 A0
111 A1
110 A2
109 A3
108 A4
107 A5
106 A6
105 A7
102 A8
101 A9
115 A10
100 A11
www.xilinx.com
at the SODIMM end of the interface. The SODIMM provides a
XC4VLX25 SODIMM
U10 Pin # J4 Pin #
AE21 89
V6 91
AE18 96
W1 95
AF18 12
W2 26
AF22 48
AD23 62
AF21 134
AD22 148
V5 170
AB18 184
Chapter 3: Hardware Description
Table 3-2
XC4VLX25
Signal
U10 Pin #
CK2 AC25
CK2_B AC26
CKE0 AC18
CKE1 AB23
DM0
DM1 AA18
DM2 AB21
DM3
DM4
DM5
DM6
DM7
Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
Y19
Y17
AF5
AD4
Y10
AE6