Creating The Gtx Ibert Core - Xilinx Virtex-7 FPGA VC7203 Characterization Kit IBERT Getting Started Manual

Table 1-2: Si570 and Si5368 Frequency Table (Cont'd)
Address Protocol
92 Generic
93 Generic
94 Generic
95 Generic
96 Generic
97 Generic
98 Generic
99 Generic
100 Generic
101 Generic
102 Generic

Creating the GTX IBERT Core

Vivado Design Suite version 2013.3 is required to rebuild the designs shown here.
This section provides a procedure to create a single Quad GTX IBERT core with integrated
SuperClock-2 controller. The procedure assumes Quad 113 and 12.5 Gb/s line rate, but
cores for any of the GTX Quads with any supported line rate can be created following the
same series of steps.
For more details on generating IBERT cores, refer to Vivado Design Suite User Guide:
Programming and Debugging (UG908).
1.
VC7203 IBERT Getting Started Guide
UG847 (v4.0) November 6, 2013
Frequency
Address
(MHz)
310.000 105
315.000 106
320.000 107
325.000 108
330.000 109
335.000 110
340.000 111
345.000 112
350.000 113
355.000 114
360.000 115
Start the Vivado Design Suite.
www.xilinx.com
Frequency
Protocol
(MHz)
Generic 375.000
Generic 380.000
Generic 385.000
Generic 390.000
Generic 395.000
Generic 400.000
Generic 405.000
Generic 410.000
Generic 415.000
Generic 420.000
Generic 425.000
Creating the GTX IBERT Core
Frequency
Address Protocol
(MHz)
118 Generic 440.000
119 Generic 445.000
120 Generic 450.000
121 Generic 455.000
122 Generic 460.000
123 Generic 465.000
124 Generic 470.000
125 Generic 475.000
126 Generic 480.000
127 Generic 485.000
Send Feedback
25