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Introduction to the PPC405
The PPC405 is a 32-bit implementation of the PowerPC
that is derived from the PowerPC architecture. Specifically, the PPC405 is an embedded
PowerPC 405D5 processor core.
The PowerPC architecture provides a software model that ensures compatibility between
implementations of the PowerPC family of microprocessors. The PowerPC architecture
defines parameters that guarantee compatible processor implementations at the
application-program level, allowing broad flexibility in the development of derivative
PowerPC implementations that meet specific market requirements.
This chapter provides an overview of the PowerPC architecture and an introduction to the
features of the PPC405 core.
PowerPC Architecture Overview
The PowerPC architecture is a 64-bit architecture with a 32-bit subset. The material in this
document only covers aspects of the 32-bit architecture implemented by the PPC405.
In general, the PowerPC architecture defines the following:
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Instruction Set
The instruction set specifies the types of instructions (such as load/store, integer arithmetic,
and branch instructions), the specific instructions, and the encoding used for the
instructions. The instruction set definition also specifies the addressing modes used for
accessing memory.
Programming Model
The programming model defines the register set and the memory conventions, including
details regarding the bit and byte ordering, and the conventions for how data are stored.
Memory Model
The memory model defines the address-space size and how it is subdivided into pages. It
also defines attributes for specifying memory-region cacheability, byte ordering (big-
endian or little-endian), coherency, and protection.
March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
Instruction set
Programming model
Memory model
Exception model
Memory-management model
Time-keeping model
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