Data Alu; Address Generation Unit; Program Control Unit; Section 2.4 Data Alu - Motorola DSP56000 Manual

ory spaces are addressed over a single 16-bit unidirectional address bus driven by a
three-input multiplexer that can select the XAB, the YAB, or the PAB. Only one external
memory access can be made in an instruction cycle. There is no speed penalty if only one
external memory space is accessed in an instruction cycle. However, if two or three ex-
ternal memory spaces are accessed in a single instruction, there will be a one or two
instruction cycle execution delay, respectively.
A bus arbitrator controls external access.
2.3.1 Internal Bus Switch
Transfers between buses occur in the internal bus switch. The internal bus switch, which
is similar to a switch matrix, can connect any two internal buses without adding any pipe-
line delays. This flexibility simplifies programming.
2.3.2 Bit Manipulation Unit
The bit manipulation unit is physically located in the internal bus switch block because the
internal data bus switch can access each memory space. The bit manipulation unit per-
forms bit manipulation operations on memory locations, address registers, control
registers, and data registers over the XDB, YDB, and GDB.
2.4

DATA ALU

The data ALU performs all of the arithmetic and logical operations on data operands. It
consists of four 24-bit input registers, two 48-bit accumulator registers, two 8-bit accumu-
lator extension registers, an accumulator shifter, two data bus shifter/limiter circuits, and
a parallel, single-cycle, nonpipelined Multiply-Accumulator (MAC) unit.
2.5

ADDRESS GENERATION UNIT

The AGU performs all of the address storage and address calculations necessary to indi-
rectly address data operands in memory. It operates in parallel with other chip resources
to minimize address generation overhead. The AGU has two identical address arithmetic
units that can generate two 16-bit addresses every instruction cycle. Each of the arith-
metic units can perform three types of arithmetic: linear, modulo, and reverse-carry.
2.6

PROGRAM CONTROL UNIT

The program control unit performs instruction prefetch, instruction decoding, hardware
DO loop control, and interrupt (or exception) processing. It consists of three components:
the program address generator, the program decode controller, and the program interrupt
controller. It contains a 15-level by 32-bit system stack memory and the following six di-
MOTOROLA DSP56K CENTRAL ARCHITECTURE OVERVIEW
DATA ALU
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