Headers And Test Connections; Versa Headers; Table 8.1. Versa J8 Header Pin Connections - Lattice Semiconductor MachXO5-NX User Manual

8. Headers and Test Connections

This section describes the MachXO5-NX Development Board headers and test connections.

8.1. Versa Headers

The board provides two headers, J8 and J9, for expansion purpose.

Table 8.1. Versa J8 Header Pin Connections

J8 Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02052-0.90
Net Name
GND
NC
EXPCON_2V5*
EXPCON_IO29
EXPCON_IO30
EXPCON_IO31
EXPCON_IO32
EXPCON_IO33
EXPCON_IO34
EXPCON_IO35
EXPCON_IO36
EXPCON_IO37
EXPCON_IO38
EXPCON_IO39
EXPCON_IO40
EXPCON_IO41
EXPCON_IO42
EXPCON_IO43
EXPCON_IO44
EXPCON_IO45
5VIN*
GND
EXPCON_2V5*
GND
+3.3V
GND
+3.3V
GND
EXPCON_OSC
GND
EXPCON_CLKIN
GND
EXPCON_CLKOUT
GND
EXPCON_3V3**
GND
EXPCON_3V3**
GND
EXPCON_3V3**
GND
MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
MachXO5-25 Ball Location
—
—
—
C20
H14
G14
H15
G18
H16
G19
H20
H19
J17
J18
J15
J16
J13
J14
J12
H13
—
—
—
—
—
—
—
—
E16
—
E17
—
D20
—
—
—
—
—
—
—
21