Pci Express Power Interface; Programming/Fpga Configuration; Ispvm Download Interface - Lattice Semiconductor LatticeECP2M SERDES User Manual

Lattice Semiconductor
Table 1. Board Power Supply Fuses (see Appendix A, Figure 4)
Table 2. Board Power Supply Indicators (see Appendix A, Figure 4)
External power can be supplied via the screw-terminals (TB1) as an alternative.
Table 3. Board Supply Disconnects (see Appendix A, Figure 3)

PCI Express Power Interface

Power can be sourced to the board via the PCB edge-finger (CN1). This interface allows the user to provide power
from a PCI Express Host board.

Programming/FPGA Configuration

(see Appendix A, Figure 4)
A programming header is provided on the evaluation board, providing access to the LatticeECP2M JTAG port.
Note: An ispDOWNLOAD
chased separately from Lattice.

ispVM Download Interface

J8 is an 10-pin JTAG connector used in conjunction with the ispVM USB download cable to program and control
the device.
F1
F2
F3
F4
F5
F6
D1 2.5V Source Good Indicator
D2 3.3V Source Good Indicator
D3 12V Input Good Indicator
D4 1.2V VCC Core Source Good Indicator
D5 1.5V Source Good Indicator
D6 1.8V Source Good Indicator
D7 1.2V Source Good Indicator
Screw terminal for 12 VDC
TB1 Pin1(square PCB pad) -> +12V DC
Pin2 -> Ground
®
Cable is included with each ispLEVER design tool shipment. Cables may also be pur-
Evaluation Board User's Guide
1.2V Core Fuse
1.5V Fuse
3.3V Fuse
1.2V Fuse
2.5V Fuse
1.8V Fuse
5
LatticeECP2M SERDES