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13 I
2
C (I2C)
Note: If the I2CnCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being
sent/received cannot be guaranteed. When setting the I2CnCTL.MODEN bit to 1 again after
that, be sure to write 1 to the I2CnCTL.SFTRST bit as well.
I2C Ch.n Transmit Data Register
Register name
Bit
I2CnTXD
15–8 –
7–0 TXD[7:0]
Bits 15–8 Reserved
Bits 7–0
TXD[7:0]
Data can be written to the transmit data buffer through these bits. Make sure the I2CnINTF.TBEIF bit
is set to 1 before writing data.
Note: Be sure to avoid writing to the I2CnTXD register when the I2CnINTF.TBEIF bit = 0, otherwise
transmit data cannot be guaranteed.
I2C Ch.n Receive Data Register
Register name
Bit
I2CnRXD
15–8 –
7–0 RXD[7:0]
Bits 15–8 Reserved
Bits 7–0
RXD[7:0]
The receive data buffer can be read through these bits.
I2C Ch.n Status and Interrupt Flag Register
Register name
Bit
I2CnINTF
15–13 –
12
11
10
9
8
7
6
5
4
3
2
1
0
Bits 15–13 Reserved
Bit 12
SDALOW
This bit indicates that SDA is set to low level.
1 (R):
SDA = Low level
0 (R):
SDA = High level
Bit 11
SCLLOW
This bit indicates that SCL is set to low level.
1 (R):
SCL = Low level
0 (R):
SCL = High level
13-20
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
0x00
Bit name
Initial
0x0
SDALOW
0
SCLLOW
0
BSY
0
TR
0
–
0
BYTEENDIF
0
GCIF
0
NACKIF
0
STOPIF
0
STARTIF
0
ERRIF
0
RBFIF
0
TBEIF
0
Seiko Epson Corporation
Reset
R/W
–
R
–
H0
R/W
Reset
R/W
–
R
–
H0
R
Reset
R/W
–
R
–
H0
R
H0
R
H0/S0
R
H0
R
–
R
H0/S0
R/W
Cleared by writing 1.
H0/S0
R/W
H0/S0
R/W
H0/S0
R/W
H0/S0
R/W
H0/S0
R/W
H0/S0
R
Cleared by reading the I2CnRXD reg-
ister.
H0/S0
R
Cleared by writing to the I2CnTXD
register.
S1C17M12/M13 TECHNICAL MANUAL
Remarks
Remarks
Remarks
(Rev. 1.2)
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