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11 SUPPLY VOLTAGE DETECTOR (SVD2)
11.2 Input Pin and External Connection
11.2.1 Input Pin
Table 11.2.1.1 shows the SVD2 input pin.
Pin name
EXSVDn
If the port is shared with the EXSVDn pin and other functions, the EXSVDn function must be assigned to the port
before SVD2 Ch.n can be activated. For more information, refer to the "I/O Ports" chapter.
11.2.2 External Connection
Figure 11.2.2.1 Connection between EXSVDn Pin and External Power Supply
R
resistance value must be determined so that it will be sufficiently smaller than the EXSVDn input impedance
EXT
R
. For the EXSVDn pin input voltage range and the EXSVDn input impedance, refer to "Supply Voltage De-
EXSVD
tector Characteristics" in the "Electrical Characteristics" chapter.
11.3 Clock Settings
11.3.1 SVD2 Operating Clock
When using SVD2 Ch.n, the SVD2 Ch.n operating clock CLK_SVD2_n must be supplied to SVD2 Ch.n from the
clock generator.
The CLK_SVD2_n supply should be controlled as in the procedure shown below.
1. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)
2. Enable the clock source in the clock generator if it is stopped (refer to "Clock Generator" in the "Power Supply,
Reset, and Clocks" chapter).
3. Set the following SVD2_nCLK register bits:
- SVD2_nCLK.CLKSRC[1:0] bits
- SVD2_nCLK.CLKDIV[2:0] bits
4. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection)
The CLK_SVD2_n frequency should be set to around 32 kHz.
11.3.2 Clock Supply in SLEEP Mode
When using SVD2 Ch.n during SLEEP mode, the SVD2 Ch.n operating clock CLK_SVD2_n must be configured
so that it will keep supplying by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_SVD2_n clock source.
If the CLGOSC.xxxxSLPC bit for the CLK_SVD2_n clock source is 1, the CLK_SVD2_n clock source is deac-
tivated during SLEEP mode and SVD2 Ch.n stops with the register settings maintained at those before entering
SLEEP mode. After the CPU returns to normal mode, CLK_SVD2_n is supplied and the SVD2 Ch.n operation re-
sumes.
11-2
Table 11.2.1.1 SVD2 Input Pin
I/O*
Initial status*
A
A (Hi-Z)
EXSVDn
External power
supply, etc.
Seiko Epson Corporation
SVD2 Ch.n external voltage detection input pin
* Indicates the status when the pin is configured for SVD2.
SVD
analog block
R
EXSVD
V
SS
(Clock source selection)
(Clock division ratio selection = Clock frequency setting)
Function
S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
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