B&R Automation PC 3100 User Manual page 163

4.1.7.2.9.1 PCI Express configuration
BIOS parameter
PCI Express clock gating
Legacy IO low latency
DMI link ASPM control
PCIE port assigned to LAN
Port8xh decode
Peer memory write enable
Compliance test mode
PCIe USB glitch W/A
1)
PCIe function swap
PCI Express Gen3 eq lanes
PCI Express root port n
3)
Table 189: Advanced - PCH-IO configuration - PCI Express configuration
1) PCIe-USB glitch workaround
2) PCIe for graphics
3) Depending on the hardware, all available PCIe root ports are listed.
PCI Express Gen3 eq lanes
BIOS parameter
PCIEn Cm
1)
PCIEn Cp
1)
Override SW EQ setting
Coeffq Cp
2)
Coeffq Cm
2)
Table 190: Advanced - PCH-IO configuration - PCI Express configuration - PCI Express Gen3 Eq Lanes
1) n is the number of available PCIe root ports.
2) q ranges from 0 to 5.
PCI Express root port n
BIOS parameter
PCI Express root port n
1)
Topology
ASPM
L1 substates
Gen3 Eq Phase3 Method
UPTP
2)
DPTP
3)
ACS
4)
Table 191: Advanced - PCH-IO configuration - PCI Express root port n
Automation PC 3100 User's manual V 1.00 Translation of the original documentation
Setting options Description
Disabled Disables/Enables PCI Express clock gating for root ports
Enabled
Disabled Disables/Enables legacy IO low latency
Enabled
Disabled Disables/Enables DMI link ASPM control
Enabled
- Displays the PCIe port assigned to the LAN
Disabled Disables/Enables Port8xh decoding
Enabled
Disabled Disables/Enables peer memory write enable
Enabled
Disables/Enables compliance test mode
Disabled
Enabled
Disabled Disables/Enables PCIe USB glitch W/A
For faulty USB devices after the PCIe/PEG
Enabled
Disabled Disables/Enables PCIe function swap
Enabled
Enter Opens submenu
Enter Opens submenu
Setting options Description
INT Defines PCIE n Cm
Default: 6 Range: 0 to 63
INT Defines PCIE n Cp
Default: 2 Range: 0 to 63
Disabled Disables/Enables SW EQ setting override
Enabled
INT Defines q Cp
Default: (Diverse) Range: 0 to 63
INT Defines q Cm
Default: 2 Range: 0 to 63
Setting options Description
Disabled Disables/Enables PCI Express root port n
Enabled
x4 Selects the PCIe root port topology
Unknown
x1
SATA Express
M2
Auto Selects PCIe Active State Power Management manually/automatically or disables it
Disabled
L0sL1
L0s
L1
Disabled Selects or disables L1 substates
L1.1
L1.2
L1.1 & L1.2
Hardware PCIe Gen3 equalization Phase3 method
Software search
Static coeff.
INT Selects the UPT preset
Default: 5 Range: 0 to 10
INT Selects the DPT preset
Default: 7 Range: 0 to 10
Disabled Disables/Enables access control services extended capabilities
Enabled
port
2)
"PCI Express Gen3 eq lanes" on page 163
"PCI Express root port n" on page 163
Software
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