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(4) Reception completion processing by a slave
During processing of reception completion by a slave device (interrupt servicing etc.), confirm the status of bit
3 (CMDD) of the serial bus interface control register (SBIC) and bit 6 (COI) of serial operating mode register 0
(CSIM0) (when CMDD = 1). This procedure is necessary to use the wake-up function normally, because if an
uncertain amount of data is sent from the master device, the slave device cannot determine whether the start
condition signal or data will be sent from the master. This may disable use the wake-up function.
16.4.7 Restrictions on use of I
The µ PD78014Y subseries devices have the following restrictions.
(1) Restriction on master device operation in the I
Applied device:
Description:
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
2
C bus mode
µ PD78P014Y
IE-78014-R-EM
When the master device outputs the serial clock via the SCL pin, if the SCL rise time takes
more than 1/32 of serial clock period, then the master device sometimes suspends serial clock
output or outputs impulse signal via the SCL pin.
"Rise time" is the period of time that elapses between the moment which the master device
starts communication and the moment which the potential of SCL rises to 0.8V
a period during which the slave device outputs the wait signal by keeping the SCL pin at low
level although the master device is ready for communication is included in the "rise time".
2
C bus mode
. Therefore
DD
403
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