ST STM32G4 Series Reference Manual page 314

Reset and clock control (RCC)
Bit 5 TIM7EN: TIM7 timer clock enable
Bit 4 TIM6EN: TIM6 timer clock enable
Bit 3 TIM5EN: TIM5 timer clock enable
Bit 2 TIM4EN: TIM4 timer clock enable
Bit 1 TIM3EN: TIM3 timer clock enable
Bit 0 TIM2EN: TIM2 timer clock enable
7.4.18 APB1 peripheral clock enable register 2 (RCC_APB1ENR2)
Address offset: 0x5C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
314/2126
Set and cleared by software.
0: TIM7 clock disabled
1: TIM7 clock enabled
Set and cleared by software.
0: TIM6 clock disabled
1: TIM6 clock enabled
Set and cleared by software.
0: TIM5 clock disabled
1: TIM5 clock enabled
Set and cleared by software.
0: TIM4 clock disabled
1: TIM4 clock enabled
Set and cleared by software.
0: TIM3 clock disabled
1: TIM3 clock enabled
Set and cleared by software.
0: TIM2 clock disabled
1: TIM2 clock enabled
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
UCPD1
Res. Res.
EN
rw
RM0440 Rev 4
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
RM0440
17 16
Res. Res.
1 0
LP
I2C4EN UART1
EN
rw rw