Display Edma Event Generation; Edma Size And Threshold Restrictions - Texas Instruments TMS320DM648 User Manual

Video port/vcxo interpolated control (vic) port
Hide thumbs Also See for TMS320DM648:
Table of Contents

Advertisement

www.ti.com

2.3.2 Display EDMA Event Generation

Display EDMA events are generated based on the amount of room available in the FIFO. The VDTHRLDn
value indicates the level at which the FIFO has room to receive another EDMA. If the FIFO has at least
VDTHRLDn locations available, a EDMA event is generated. Once an E EDMA event has been
requested, another EDMA event may not be generated until the servicing of the first EDMA event has
begun (as indicated by the first write to the FIFO by the EDMA event service). If there is at least 2x the
threshold space still available in the FIFO after the first EDMA service is begun (and the display event
counter has not expired) then another EDMA event may be generated. Thus, up to one EDMA request
may be outstanding.
An incoming data counter is loaded with the VDTHRLDn (or VDTHRLDn/2 for Cb and Cr FIFOs) value at
the beginning of each EDMA event service and counts down the incoming EDMA double words When the
counter reaches 0, the EDMA event is complete.
An EDMA event counter is used to track the number of EDMA events generated in each field as
programmed in the VDDISPEVT register. The DISPEVT1 or DISPEVT2 value (depending on the current
display field) is loaded at the start of each field. The event counter then decrements with each EDMA
event generation until it reaches 0, at which point no more EDMA events are generated until the next field
begins. Once the last line of data for a field has been requested, the EDMA logic stops generating events
until the field is complete in case the CPU needs to modify the EDMA address pointers.
For BT.656 and Y/C modes, there are three FIFOs, one for each of the Y, Cb, and Cr color components.
Each FIFO generates its own EDMA event; therefore, the EDMA event state and FIFO thresholds for each
FIFO are tracked independently. (The Cb and Cr FIFOs use a threshold value of 1/2 VDTHRLD).

2.3.3 EDMA Size and Threshold Restrictions

The video port FIFOs are 64-bits wide and always read or write 64 bits at a time. For this reason, EDMA
accesses must always be an even number of words in length. It is expected that in most cases the
threshold size is set to the line length (rounded up to the next double word). This always works because
different lines are not packed together within a double word and the Cb and Cr thresholds
(1/2 VCTHRLDx/VDTHRLD) are always rounded up to the double word.
For example, in 8-bit BT.656 capture mode with a line length of 712 (Y), setting the threshold to the line
length results in a VCTHRLD of 712 pixels x 1 bytes/pixel x double word/8 bytes = 89 double words. The
Cb and Cr FIFOs contain half the data (44.5 double words) so their thresholds are set to 45 double words.
Therefore, the Cb and Cr EDMAs each transmit an extra 4 bytes at the end of each line.
If a multi-horizontal line length threshold is desired (2 lines, for example) then the chosen line length must
round up to an even number of double words so that it is evenly divisible by 2. If this is not the case, then
the Cb and Cr FIFO transfers are corrupted. For the multiline case, consider the same 8-bit BT.656
capture mode with a line length of 712 (Y). If the threshold is set for 2 lines, this results in a VCTHRLD
value of 2 x 89 = 178 double words. The actual Cb/Cr line length is 44.5 double words that requires a
length of 45. To transfer 2 lines requires 2 x 45 = 90 double words. However, for this VCTHRLD, the
EDMA logic would calculate the Cb/Cr threshold size as 178/2 = 89 double words, which is 1 double word
off. This can be corrected by increasing the line length to 720 pixels (and ignoring the extra captured
pixels) or decreasing it to 704 pixels.
Similarly if a sub-horizontal line length is desired (1/2 line, for example), then the line length and threshold
must be chosen such that the threshold is divisible by 2. (This can also be stated as the line length must
be an even multiple of #EDMAs/line x 8). For the subline case, consider the 8-bit BT.656 capture mode
with a line length of 624 (Y). If the threshold is set for 1/2 the line length, this results in VCTHRLD =
(624/2)/8 = 39 double words. The EDMA logic would calculate the Cb/Cr threshold as 39/2 = 20 double
words. However, two such Cb/Cr EDMA events would result in a transfer of 40 double words, which is
larger than the actual Cb/Cr line length of (624/2)/8 = 39 double words. This can be corrected by changing
the line size to 640 pixels or 608 pixels, or by changing the threshold to be 1/3 the line length (VCTHRLD
= (624/3)/8 = 26 double words and the Cb/Cr threshold is 26/2 = 13 double words. 3 x 13 = 39 double
words, which is exactly the Cb/Cr line length.)
SPRUEM1 – May 2007
Submit Documentation Feedback
EDMA Operation
Video Port
33

Advertisement

Table of Contents
loading

This manual is also suitable for:

Tms320dm647

Table of Contents