Timing Registers; Xrevision Register; Xintf Configuration And Control Register Mappings; Xrevision Register Bit Definitions - Texas Instruments SM320F2812-HT Data Manual

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The operation and timing of the external interface, can be controlled by the registers listed in
Table 3-8. XINTF Configuration and Control Register Mappings
NAME ADDRESS
XTIMING0 0x00 0B20
XTIMING1 0x00 0B22
XTIMING2 0x00 0B24
XTIMING6 0x00 0B2C
XTIMING7 0x00 0B2E
XINTCNF2 0x00 0B34
XBANK 0x00 0B38
XREVISION 0x00 0B3A

3.5.1 Timing Registers

XINTF signal timing can be tuned to match specific external device requirements such as setup and hold
times to strobe signals for contention avoidance and maximizing bus efficiency. The timing parameters
can be configured individually for each zone. This allows the programmer to maximize the efficiency of the
bus, based on the type of memory or peripheral that the user needs to access. All XINTF timing values
are with respect to XTIMCLK, which is equal to or one-half of the SYSCLKOUT rate, as shown in Figure
6-27.
For detailed information on the XINTF timing and configuration register bit fields, see the TMS320x281x
DSP External Interface (XINTF) Reference Guide (SPRU067).

3.5.2 XREVISION Register

The XREVISION register contains a unique number to identify the particular version of XINTF used in the
product. For the F2812, this register is configured as described in
BIT(S) NAME
15-0 REVISION
Copyright © 2009–2011, Texas Instruments Incorporated
SIZE (×16)
XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit
2
register
XINTF Timing Register, Zone 1 can access as two 16-bit registers or one 32-bit
2
register
XINTF Timing Register, Zone 2 can access as two 16-bit registers or one 32-bit
2
register
XINTF Timing Register, Zone 6 can access as two 16-bit registers or one 32-bit
2
register
XINTF Timing Register, Zone 7 can access as two 16-bit registers or one 32-bit
2
register
XINTF Configuration Register can access as two 16-bit registers or one 32-bit
2
register
1 XINTF Bank Control Register
1 XINTF Revision Register
Table 3-9. XREVISION Register Bit Definitions
TYPE RESET
Current XINTF Revision. For internal use/reference. Test purposes only.
R 0x0004
Subject to change.
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SGUS062B – JUNE 2009 – REVISED JUNE 2011
DESCRIPTION
Table 3-9.
DESCRIPTION
SM320F2812-HT
SM320F2812-HT
Table 3-8.
Functional Overview 39