Timing Considerations; Hit Time - Texas Instruments TMS320VC5501 Instruction Cache

4

Timing Considerations

4.1

Hit Time

SPRU630C
As the I-Cache fetches and returns 32-bit words requested by the CPU, two
key time periods affect the speed of the I-Cache:
Hit time
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Miss penalty
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The hit time is the time required for the I-Cache to deliver the 32-bit requested
word to the CPU in the case of a hit (when the word is present in the I-Cache).
The hit time is either 1 or 2 CPU clock cycles:
An initial request (a request that follows a period of inactivity) has a hit
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time of 2 cycles.
Subsequent requests have a hit time of 1 cycle if:
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The requests are consecutive (no inactivity in between) and
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The requests are to sequential addresses
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Subsequent requests have a hit time of 2 cycles if:
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The requests are not consecutive or
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The requests are to nonsequential addresses
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Timing Considerations
Instruction Cache 19