Writing To The Fifo; Reading From The Fifo; Tci Fifo Packing; Tci Timestamp Format (Little Endian) - Texas Instruments TMS320DM648 User Manual

Video port/vcxo interpolated control (vic) port
Hide thumbs Also See for TMS320DM648:
Table of Contents

Advertisement

TCI Capture Mode
VCACTL Bit
CON
FRAME
0
1
1
0
1
1

3.8.6 Writing to the FIFO

The captured TCI packet data and the associated time stamps are written into the receive FIFO. The
packet data is written first, followed by the timestamp. The FIFO controller controls both data writes and
timestamp writes into the FIFO. The FIFO data packing is shown in
VDIN[9−2]
63
TSI 15
TSI 7
TSI FIFO
The data capture circuitry signals to the synchronizing circuit when to take a timestamp of the hardware
counters. The FIFO write controller keeps track of the number of bytes received in a packet. It multiplexes
the timestamp data and the packet data onto the FIFO write data bus. The timestamp and packet error
information are inserted after each packet in the FIFO .The format for the timestamp is shown in
Figure
3-19.
63
62
61
PERR
PSTERR
31

3.8.7 Reading from the FIFO

The YSRCA location is associated with the TCI capture buffer. The YSRCA location is a read-only
pseudo-register and is used to access the TCI data samples stored in the buffer.
The captured data packet size is set by VCASTOP. The VCXSTOP and VCYSTOP bits set the 24-bits of
TCI packet size (VCXSTOP sets the lower 12 bits and VCYSTOP sets the upper 12 bits). Capture is
complete and the FRMC bit is set when the data counter equals the combined VCYSTOP and VCXSTOP
value.
66
Video Capture Port
Table 3-12. TCI Capture Mode Operation (continued)
CF2
CF1
x
x
x
x
x
x
Figure 3-18. TCI FIFO Packing
VCLKIN
TSI 0
TSI 1
TSI 2
56 55
48 47
40 39
TSI 14
TSI 13
TSI 6
TSI 5
Figure 3-19. TCI Timestamp Format (Little Endian)
Reserved
Operation
Single packet capture. FRMC is set after packet capture and causes CCMPA
to be set. Capture is halted until the FRMC bit is cleared.
Continuous packet capture. FRMC is set after packet capture and causes
CCMPA to be set (CCMPx interrupt can be disabled). The port will continue
capturing packets regardless of the state of FRMC.
Reserved
Figure
TSI 3
TSI 4
TSI 5
TSI 6
TSI 7
32
31
24 23
TSI 12
TSI 11
TSI 10
TSI 4
TSI 3
Little-Endian Packing
42
PCR
3-18.
TSI 8
TSI 9
TSI 10
TSI 11
16 15
8 7
TSI 9
TSI 8
TSI 2
TSI 1
TSI 0
41
PCR extension
SPRUEM1 – May 2007
Submit Documentation Feedback
www.ti.com
0
33
32
PCR
0

Advertisement

Table of Contents
loading

This manual is also suitable for:

Tms320dm647

Table of Contents