Ddr2 Memory Controller Interface; Ddr2 Memory Controller Fifo Block Diagram; Ddr2 Memory Controller Fifo Description - Texas Instruments TMS320C642x DSP User Manual

Peripheral Architecture
2.8

DDR2 Memory Controller Interface

To move data efficiently from on-chip resources to external DDR2 SDRAM memory, the DDR2 memory
controller makes use of a command FIFO, a write FIFO, a read FIFO, and command and data schedulers.
Table 11 describes the purpose of each FIFO.
Figure 14 shows the block diagram of the DDR2 memory controller FIFOs. Commands, write data, and
read data arrive at the DDR2 memory controller parallel to each other. The same peripheral bus is used to
write and read data from external memory as well as internal memory-mapped registers.
FIFO Description
Command Stores all commands coming from on-chip requestors
Write Stores write data coming from on-chip requestors to memory
Read Stores read data coming from memory to on-chip requestors
26 DDR2 Memory Controller
Table 11. DDR2 Memory Controller FIFO Description
Figure 14. DDR2 Memory Controller FIFO Block Diagram
Command FIFO
Write FIFO
Read FIFO
Command
Data
Depth (64-bit doublewords)
7
11
17
Command/Data
Command
Scheduler
to Memory
Write Data
to Memory
Read Data
from
Memory
Registers
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SPRUEM4A – November 2007