General-Purpose Input/Output (Gpio); Gpio - Output Timing; Example Of Effect Of Writing Into Pllcr Register; General-Purpose Output Switching Characteristics - Texas Instruments TMS320F2809 Data Manual

Digital signal processors
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Figure 6-10
shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating
frequency, OSCCLK x 4.
OSCCLK
SYSCLKOUT
OSCCLK * 2
(Current CPU
Frequency)
Figure 6-10. Example of Effect of Writing Into PLLCR Register
6.9

General-Purpose Input/Output (GPIO)

6.9.1 GPIO - Output Timing

Table 6-14. General-Purpose Output Switching Characteristics
t
Rise time, GPIO switching low to high
r(GPO)
t
Fall time, GPIO switching high to low
f(GPO)
t
Toggling frequency, GPO pins
fGPO
GPIO
Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s):
Write to PLLCR
OSCCLK/2
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, t
131072 OSCCLK Cycles Long.)
PARAMETER
t
f(GPO)
Figure 6-11. General-Purpose Output Timing
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TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230N – OCTOBER 2003 – REVISED MAY 2012
(Changed CPU Frequency)
) is
p
All GPIOs
All GPIOs
t
OSCCLK * 4
MIN
MAX
UNIT
8
8
25
MHz
r(GPO)
Electrical Specifications
ns
ns
109

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