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2.2.49 SHLL (shift logical left)
Operation
Rd (shifted logical left ) → Rd
Assembly-Language Format
SHLL Rd
Operand Size
Byte
Condition Code
I
H
— —
—
—
I:
Previous value remains unchanged.
H:
Previous value remains unchanged.
N:
Set to 1 when the result is negative; otherwise cleared to 0.
Z:
Set to 1 when the result is zero; otherwise cleared to 0.
V:
Cleared to 0.
C:
Receives the previous value in bit 0.
Description
This instruction shifts an 8-bit general register one bit to the left. The least significant bit is
cleared to 0. The most significant bit shifts into the carry flag.
The operation is shown schematically below.
MSB
C
Bit 7
The SHLL instruction is identical to the SHAL instruction except for its effect on the overflow
(V) flag.
N
Z
V
C
∆
∆
—
0
LSB
0
Bit 0
115
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