Appendix C: Xilinx Design Constraints; Overview - Xilinx ML605 Hardware User's Manual

Xilinx Design Constraints

Overview

The Xilinx Design Constraints (UCF) file template provides for designs targeting the
ML605 evaluation board. Net names in the constraints correlate with net names on the
latest ML605 evaluation board schematic. Identify the appropriate pins and replace the net
names with net names in the user RTL.
See the Constraints Guide (UG625)
The FMC connectors J63 (LPC) and J64 (HPC) are connected to 2.5V Vcco banks. Because
each user's FMC card implements customer-specific circuitry, the FMC bank I/O
standards must be uniquely defined by each customer.
Note: The latest version of the Xilinx constraint file can be found on the
ML605 Evaluation Kit
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019
[Ref 25] for more information.
website.
www.xilinx.com
Appendix C
Virtex-6 FPGA
83
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