Appendix C: Xilinx Design Constraints - Xilinx VC709 User Manual

Xilinx Design Constraints
The VC709 board Xilinx design constraints (XDC) file template provides for designs targeting the
VC709 board. Net names in the constraints correlate with net names on the latest VC709 board
schematic. Users must identify the appropriate pins and replace the net names listed here with net
names in the user RTL. See the Vivado Design Suite User Guide Using Constraints (UG903)
[Ref 10]
The FMC connector J35 is connected to 1.8V V
implements customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by
each customer.
Refer to the boards file on the Virtex-7 FPGA VC709 Evaluation Kit documentation page
(www.xilinx.com/vc709), for the latest version of the FPGA xdc constraint file.
VC709 Evaluation Board
UG887 (v1.6) March 11, 2019
for more information.
www.xilinx.com
Appendix C
banks. Because each user's FMC card
CCO
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