Xilinx ML605 Hardware User's Manual page 36

Chapter 1: ML605 Evaluation Board
Table 1-8
transceivers to the Virtex-6 FPGA Integrated Endpoint block for PCIe designs.
Table 1-8: PCIe Edge Connector Connections
U1 FPGA
Schematic Net Name
Pin
F1 PCIE_TXO_P
F2 PCIE_TXO_N
H1 PCIE_TX1_P
H2 PCIE_TX1_N
K1 PCIE_TX2_P
K2 PCIE_TX2_N
M1 PCIE_TX3_P
M2 PCIE_TX3_N
P1 PCIE_TX4_P
P2 PCIE_TX4_N
T1 PCIE_TX5_P
T2 PCIE_TX5_N
V1 PCIE_TX6_P
V2 PCIE_TX6_N
Y1 PCIE_TX7_P
Y2 PCIE_TX7_N
J3 PCIE_RXO_P
J4 PCIE_RXO_N
K5 PCIE_RX1_P
K6 PCIE_RX1_N
L3 PCIE_RX2_P
L4 PCIE_RX2_N
N3 PCIE_RX3_P
N4 PCIE_RX3_N
R3 PCIE_RX4_P
R4 PCIE_RX4_N
U3 PCIE_RX5_P
U4 PCIE_RX5_N
W3 PCIE_RX6_P
W4 PCIE_RX6_N
36
Send Feedback
shows the PCIe connector (P1) that provides up to 8-lane access through the GTX
P1 PCIe Edge Connector
Pin Number Pin Name
A16 PERp0
A17 PERn0
A21 PERp1
A22 PERn1
A25 PERp2
A26 PERn2
A29 PERp3
A30 PERn3
A35 PERp4
A36 PERn4
A39 PERp5
A40 PERn5
A43 PERp6
A44 PERn6
A47 PERp7
A48 PERn7
B14 PETp0
B15 PETn0
B19 PETp1
B20 PETn1
B23 PETp2
B24 PETn2
B27 PETp3
B28 PETn3
B33 PETp4
B34 PETn4
B37 PETp5
B38 PETn5
B41 PETp6
B42 PETn6
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Description
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019
Package
Placement
GTXE1_X0Y15
GTXE1_X0Y14
GTXE1_X0Y13
GTXE1_X0Y12
GTXE1_X0Y11
GTXE1_X0Y10
GTXE1_X0Y9
GTXE1_X0Y8
GTXE1_X0Y15
GTXE1_X0Y14
GTXE1_X0Y13
GTXE1_X0Y12
GTXE1_X0Y11
GTXE1_X0Y10
GTXE1_X0Y9