User Dip Switch - Xilinx ML605 Hardware User's Manual

Table 1-22: User Pushbutton Switch Connections
U1 FPGA Pin

User DIP Switch

The ML605 includes an active-High eight pole DIP switch as described in
Table
X-Ref Target - Figure 1-20
GPIO DIP SW1
GPIO DIP SW2
GPIO DIP SW3
GPIO DIP SW4
GPIO DIP SW5
GPIO DIP SW6
GPIO DIP SW7
GPIO DIP SW8
Table 1-23: User DIP Switch Connections
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019
Schematic Net Name
A19 GPIO_SW_N
A18 GPIO_SW_S
G17 GPIO_SW_E
H17 GPIO_SW_W
G26 GPIO_SW_C
H10 CPU_RESET
1-23.
Figure 1-20: User 8-pole DIP Switch
U1 FPGA Pin Schematic Net Name
D22
C22
L21
L20
C18
B18
K22
K21
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Pushbutton
Switch Pin
1
2
3
4
5
6
7
8
GPIO_DIP_SW1
GPIO_DIP_SW2
GPIO_DIP_SW3
GPIO_DIP_SW4
GPIO_DIP_SW5
GPIO_DIP_SW6
GPIO_DIP_SW7
GPIO_DIP_SW8
Detailed Description
SW5.2
SW6.2
SW7.2
SW8.2
SW9.2
SW10.2
Figure 1-20
VCC1V5
SW1
16
15
14
13
12
11
10
9
SDMX-8-X
UG534_20_072109
DIP Switch Pin
SW1.1
SW1.2
SW1.3
SW1.4
SW1.5
SW1.6
SW1.7
SW1.8
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