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Summary of Contents for Xilinx ML405
- Page 1 ML405 Evaluation Platform User Guide UG210 (v1.5.1) March 10, 2008...
- Page 2 Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.
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Page 3: Table Of Contents
20. Xilinx XC95144XL CPLD ........ - Page 4 Linear Flash and CPLD ........... . 34 www.xilinx.com ML405 Evaluation Platform UG210 (v1.5.1) March 10, 2008...
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Page 5: Preface: About This Guide
Preface About This Guide The ML405 evaluation platform enables designers to investigate and experiment with features of the Virtex™-4 family of FPGAs. This user guide describes features and operation of the ML405 evaluation platform. Guide Contents This manual contains the following chapters: •... -
Page 6: Online Document
Cross-reference link to a location Figure 2-5 in the Virtex-II Red text in another document Platform FPGA User Guide. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files. www.xilinx.com ML405 Evaluation Platform UG210 (v1.5.1) March 10, 2008... -
Page 7: Introduction
Chapter 1 ML405 Evaluation Platform Introduction The ML405 evaluation platform enables designers to investigate and experiment with features of the Virtex™-4 family of FPGAs. This user guide describes features and operation of the ML405 evaluation platform. Features • Virtex-4 FPGA: ♦... -
Page 8: Package Contents
10/100/1000 tri-speed Ethernet PHY transceiver • USB interface chip (Cypress CY7C67300) with host and peripheral ports • Xilinx XC95144XL CPLD to allow linear flash chips to be used for FPGA configuration • Xilinx XCF32P Platform Flash configuration storage device •... -
Page 9: Block Diagram
Introduction Block Diagram Figure 1-1 shows a block diagram of the ML405 evaluation platform (board). Host Synchronous Peripheral Controller SRAM Peripheral System ACE FLASH 10/100/1000 Controller RJ-45 Ethernet PHY FLASH DDR SDRAM Platform Flash DDR SDRAM CPLD GPIO (Pushbutton Switch/LED) -
Page 10: Detailed Description
Figure 1-2 (front) and Figure 1-3, page 11 (back). Each feature is detailed in the corresponding numbered sections that follow. ug210_02_053106 Figure 1-2: Detailed Description of Virtex-4 ML405 Evaluation Platform Components (Front) www.xilinx.com ML405 Evaluation Platform UG210 (v1.5.1) March 10, 2008... - Page 11 Detailed Description ug210_03_102405 Figure 1-3: Detailed Description of Virtex-4 ML405 Evaluation Platform Components (Back) Note: The label on the CF card shipped with your board might differ from the one shown. ML405 Evaluation Platform www.xilinx.com UG210 (v1.5.1) March 10, 2008...
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Page 12: Virtex-4 Fpga
Chapter 1: ML405 Evaluation Platform 1. Virtex-4 FPGA A Xilinx Virtex-4 FPGA, XC4VFX20-FF672-10, is installed on the evaluation platform (the board). Configuration The board supports configuration in all modes: JTAG, Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP modes. See “Configuration Options,”... -
Page 13: Ddr Sdram
DQS signals. This looped trace can be used in high-speed memory controllers to help compensate for the physical trace delays between the FPGA and DDR chips. ML405 Evaluation Platform www.xilinx.com UG210 (v1.5.1) March 10, 2008... -
Page 14: Differential Clock Input And Output With Sma Connectors
SMA_DIFF_CLK_OUT_N SMA_DIFF_CLK_OUT_P 4. Oscillator Sockets The ML405 evaluation platform has two crystal oscillator sockets, each wired for standard LVTTL-type oscillators. (A 100-MHz oscillator is pre-installed in the X1 SYSCLK socket.) These connect to the FPGA clock pins as shown in Table 1-4. -
Page 15: User And Error Leds (Active-High)
• One red LED is intended to be used for signaling error conditions, such as bus errors, but can also be used for any other purpose. On the ML405 board, the Error 2 LED is not accessible by the FPGA... -
Page 16: User Pushbutton Switches (Active-High)
Chapter 1: ML405 Evaluation Platform 8. User Pushbutton Switches (Active-High) There are five active-High user pushbutton switches available for general-purpose usage and arranged in a north-east-south-west-center orientation (only the center one is cited in Figure 1-2, page 10). Table 1-6 summarizes the user pushbutton switch connections. -
Page 17: Expansion Headers
HDR2_54 HDR2_52 HDR2_50 HDR2_36 HDR2_34 AB22 AB21 HDR2_16 HDR2_14 HDR2_64 HDR2_62 AB24 AC24 HDR2_48 HDR2_46 AD24 AD23 HDR2_24 HDR2_22 AA24 AA23 HDR2_44 HDR2_42 AA20 AA19 HDR2_32 HDR2_30 HDR2_40 HDR2_38 AC23 AC22 ML405 Evaluation Platform www.xilinx.com UG210 (v1.5.1) March 10, 2008... - Page 18 Chapter 1: ML405 Evaluation Platform Single-Ended Expansion I/O Connectors Header J6 contains 32 single-ended signal connections to the FPGA I/Os. This permits the signals on this connector to carry high-speed single-ended data. All single-ended signals on connector J6 are matched length traces. The V of these signals can be set to 2.5V or...
- Page 19 In addition to the high-speed I/O paths, additional I/O signals and power connections are available to support expansion cards plugged into the ML405 board. The 14 I/O pins from the general-purpose pushbutton switches and LEDs on the board are connected to expansion connector J3.
- Page 20 Chapter 1: ML405 Evaluation Platform Table 1-10: Additional Expansion I/O Connections (J3) J3 Pin Label FPGA Pin Description VCC5 – 5V Power Supply VCC5 – 5V Power Supply VCC5 – 5V Power Supply VCC5 – 5V Power Supply – Not Connected VCC3V3 –...
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Page 21: Stereo Ac97 Audio Codec
Stereo 12. RS-232 Serial Port The ML405 board contains one male DB-9 RS-232 serial port, allowing the FPGA to communicate serial data with another device. The serial port is wired as a host (DCE) device. Therefore, a null modem cable is normally required to connect the board to the serial port on a PC. -
Page 22: Iic Bus With 4 Kb Eeprom
Ethernet MAC address. The EEPROM write protect is disabled on the ML405 board. The IIC bus uses 2.5V signaling and can operate at up to 400 kHz. IIC bus pull-up resistors are provided on the board. -
Page 23: System Ace Controller
Detailed Description 17. System ACE Controller The Xilinx System ACE CF configuration controller allows a Type I or Type II CompactFlash card to program the FPGA through the JTAG port. Both hardware and software data can be downloaded through the JTAG port. The System ACE controller can support up to eight configuration images on a single CompactFlash card. -
Page 24: Linear Flash
20. Xilinx XC95144XL CPLD A Xilinx XC95144XL CPLD is connected to the flash memory and the FPGA configuration signals. This supports applications where flash memory programs the FPGA. The CPLD is programmed from the main JTAG chain of the board. -
Page 25: 100/1000 Tri-Speed Ethernet Phy
Detailed Description 21. 10/100/1000 Tri-Speed Ethernet PHY The ML405 evaluation platform contains a Marvell Alaska PHY device (88E1111) operating at 10/100/1000 Mb/s (Table 1-13). The board supports MII, GMII, RGMII, and SGMII interface modes with the FPGA. The PHY is connected to a Halo HFJ11-1G01E RJ-45 (or compatible) connector with built-in magnetics. -
Page 26: Usb Controller With Host And Peripheral Ports
The JTAG configuration port (J20) allows for device programming and FPGA debug. The JTAG port supports the Xilinx Parallel Cable III, Parallel Cable IV, or Platform Cable USB products. Third-party configuration products might also be available. The JTAG chain can be extended to an expansion board by setting jumper J26 accordingly. -
Page 27: Onboard Power Supplies
3.3V power supply for the video DAC. 26. AC Adapter and Input Power Switch/Jack The ML405 board ships with a 30W (5V @ 6A) AC adapter. The power connector is a 2.1 mm x 5.5 mm barrel type plug (center positive). For applications requiring additional power, such as the use of expansion cards drawing significant power, a larger AC adapter might be required. -
Page 28: Init Led
Chapter 1: ML405 Evaluation Platform 28. INIT LED The INIT LED lights upon power-up to indicate that the FPGA has successfully powered up and completed its internal power-on process. 29. DONE LED The DONE LED indicates the status of the DONE pin on the FPGA. It illuminates when the FPGA is successfully configured. -
Page 29: Sfp Connector
The transmit pair is connected directly from the FPGA to the SMA connectors while the receive pair is connected to the FPGA via series AC coupling capacitors. If a DC-coupled receive-side connection is desired, these capacitors can be replaced with 0Ω 0402-size resistors. ML405 Evaluation Platform www.xilinx.com UG210 (v1.5.1) March 10, 2008... -
Page 30: Serial-Ata Host Connectors
SATA can also be used as a convenient and low cost medium for connecting MGTs. The SATA physical interface can carry MGT signals up to 1.5 Gb/s for general-purpose usage. The board ships with a special Xilinx SATA crossover cable that is used as a loopback connection between the two SATA host connectors for: •... - Page 31 LVDS levels. The LVDS output is then multiplexed out through Series AC coupling capacitors to allow the clock input of the FPGA to set the common mode voltage. ML405 Evaluation Platform www.xilinx.com UG210 (v1.5.1) March 10, 2008...
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Page 32: Mini-Smp Connectors For Power Supply Analysis
SMA-based test equipment or cables to be connected to the Mini-SMP connectors. Note: Xilinx is not responsible for damage caused by a user attempting to solder the Mini-SMP connectors onto the board. www.xilinx.com ML405 Evaluation Platform... -
Page 33: Iic Fan Controller And Temperature Monitor
J50. For high-power operating conditions, a heatsink and/or fan can be accommodated on the board. The ML405 does not ship with a heatsink/fan unit but can accommodate one (for example, Calgreg Electronics Smart-CLIP family of heatsink/fan assemblies). -
Page 34: Platform Flash Memory
Chapter 1: ML405 Evaluation Platform The PC4 JTAG connection to the JTAG chain allows a host PC to download bitstreams to the FPGA using the iMPACT software tool. PC4 also allows debug tools such as the ChipScope™ Pro Analyzer or a software debugger to access the FPGA. - Page 35 Appendix A Board Revisions This appendix describes the major differences in revisions of the ML405 platform. Table A-1 shows the features unique to each ML405 platform. Table A-1: Differences in Board Revisions Board P/N HW-V4-ML405-US/UK/EU HW-V4-ML405-UNI-G –01 and –02 –03...
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