Sgmii Gtx Transceiver Clock Generation - Xilinx ML605 Hardware User's Manual

Chapter 1: ML605 Evaluation Board
Table 1-12: Board Connections for PHY Configuration Pins (Cont'd)
CFG5
CFG6

SGMII GTX Transceiver Clock Generation

An Integrated Circuit Systems ICS844021I chip generates a high-quality, low-jitter, 125-
MHz LVDS clock from an inexpensive 25-MHz crystal oscillator. This clock is sent to the
GTX driving the SGMII interface. Series AC coupling capacitors are also present to allow
the clock input of the FPGA to set the common mode voltage.
X-Ref Target - Figure 1-13
1
R132
DNP
1%
2
1/16W
25.000MHZ
Table 1-13
Table 1-13: Ethernet PHYConnections
40
Send Feedback
Connection on
Pin
Board Definition and Value
V 2.5V
CC
PHY_LED_RX
VDDA_SGMIICLK
1
2
X3
SGMIICLK_XTAL_OUT 3
SGMIICLK_XTAL_IN 4
GND_SGMIICLK
Figure 1-13: Ethernet SGMII Clock - 125 MHz
shows the connections and pin numbers for the PHY.
U1 FPGA Pin Schematic Net Name
AN14 PHY_MDIO
AP14 PHY_MDC
AH14 PHY_INT
AH13 PHY_RESET
AL13 PHY_CRS
AK13 PHY_COL
AP11 PHY_RXCLK
AG12 PHY_RXER
AM13 PHY_RXCTL_RXDV
AN13 PHY_RXD0
AF14 PHY_RXD1
AE14 PHY_RXD2
AN12 PHY_RXD3
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Bit[2] Bit[1]
Definition and Value
DIS_FC = 1 DIS_SLEEP = 1
SEL_BDT = 0 INT_POL = 1
VDD_SGMIICLK
ICS84402II
8
VDDA VDD
7 SGMIICLK_QO_C_P
Q0
GND
6 SGMIICLK_QO_C_N
NQ0
XTAL_OUT
5
XTAL_IN OE
U82
125.00 MHz Clock
U80 M88E1111
Pin Number
33
35
32
36
115
114
7
8
4
3
128
126
125
Bit[0]
Definition and Value
HWCFG_MD[3] = 1
75/50Ω= 0
SGMIICLK_QO_P
SGMIICLK_QO_N
UG534_13_111709
Pin Name
MDIO
MDC
INT_B
RESET_B
CRS
COL
RXCLK
RXER
RXDV
RXD0
RXD1
RXD2
RXD3
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019