Xilinx ML605 Hardware User's Manual page 67

Table 1-30
Appendix B, VITA 57.1 FMC LPC (J63) and HPC (J64) Connector
Any signal named FMC_LPC_xxxx that is wired between a U1 FPGA pin and some other
device does not appear in this table.
Table 1-30: VITA 57.1 FMC LPC Connections
J63 FMC
Schematic Net Name
LPC Pin
C2 FMC_LPC_DP0_C2M_P
C3 FMC_LPC_DP0_C2M_N
C6 FMC_LPC_DP0_M2C_P
C7 FMC_LPC_DP0_M2C_N
C10 FMC_LPC_LA06_P
C11 FMC_LPC_LA06_N
C14 FMC_LPC_LA10_P
C15 FMC_LPC_LA10_N
C18 FMC_LPC_LA14_P
C19 FMC_LPC_LA14_N
C22 FMC_LPC_LA18_CC_P
C23 FMC_LPC_LA18_CC_N
C26 FMC_LPC_LA27_P
C27 FMC_LPC_LA27_N
G2 FMC_LPC_CLK1_M2C_P
G3 FMC_LPC_CLK1_M2C_N
G6 FMC_LPC_LA00_CC_P
G7 FMC_LPC_LA00_CC_N
G9 FMC_LPC_LA03_P
G10 FMC_LPC_LA03_N
G12 FMC_LPC_LA08_P
G13 FMC_LPC_LA08_N
G15 FMC_LPC_LA12_P
G16 FMC_LPC_LA12_N
G18 FMC_LPC_LA16_P
G19 FMC_LPC_LA16_N
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019
shows the VITA 57.1 FMC LPC connections. The connector pinout is in
U1 FPGA J63 FMC
Pin LPC Pin
D1 D4
D2 D5
G3 D8
G4 D9
K33 D11
J34 D12
F30 D14
G30 D15
C33 D17
B34 D18
L29 D20
L30 D21
R31 D23
R32 D24
D26
D27
F33 H2
G33 H4
K26 H5
K27 H7
J31 H8
J32 H10
J30 H11
K29 H13
E32 H14
E33 H16
A33 H17
B33 H19
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Detailed Description
Pinout.
Schematic Net Name
FMC_LPC_GBTCLK0_M2C_P
FMC_LPC_GBTCLK0_M2C_N
FMC_LPC_LA01_CC_P
FMC_LPC_LA01_CC_N
FMC_LPC_LA05_P
FMC_LPC_LA05_N
FMC_LPC_LA09_P
FMC_LPC_LA09_N
FMC_LPC_LA13_P
FMC_LPC_LA13_N
FMC_LPC_LA17_CC_P
FMC_LPC_LA17_CC_N
FMC_LPC_LA23_P
FMC_LPC_LA23_N
FMC_LPC_LA26_P
FMC_LPC_LA26_N
FMC_LPC_PRSNT_M2C_L
FMC_LPC_CLK0_M2C_P
FMC_LPC_CLK0_M2C_N
FMC_LPC_LA02_P
FMC_LPC_LA02_N
FMC_LPC_LA04_P
FMC_LPC_LA04_N
FMC_LPC_LA07_P
FMC_LPC_LA07_N
FMC_LPC_LA11_P
FMC_LPC_LA11_N
FMC_LPC_LA15_P
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U1 FPGA
Pin
M6
M5
F31
E31
H34
H33
L25
L26
D34
C34
N28
N29
R28
R27
L33
M32
AD9
A10
B10
G31
H30
K28
J29
G32
H32
D31
D32
C32
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