Xilinx ML605 Hardware User's Manual page 14

Chapter 1: ML605 Evaluation Board
The numbered features in
Table 1-1: ML605 Features
Number
14
Send Feedback
Figure 1-2
Feature
1 Virtex-6 FPGA
2 DDR3 SODIMM
3 128 Mb Platform Flash XL
4 Linear BPI Flash
System ACE CF controller, CF
5
connector
JTAG cable connector (USB
6
Mini-B)
Clock generation
a. 200 MHz oscillator (on
backside)
7 b. Oscillator socket, single-
ended
c. SMA connectors
d. MGT REFCLK SMA
connectors
8 GTX RX/TX port
PCIe Gen1 (8-lane),
9
Gen2 (4-lane)
10 SFP connector and cage
Ethernet (10/100/1000) with
11
SGMII
USB Mini-B, USB-to-UART
12
bridge
USB-A Host, USB Mini-B
13
peripheral connectors
14 Video - DVI connector
IIC NV EEPROM, 8 Kb
15
(on backside)
Status LEDs
a. Ethernet status
16
b. FPGA INIT, DONE
c. System ACE CF status
www.xilinx.com
correlate to the features and notes listed in
Notes
XC6VLX240T-1FFG1156
Micron 512 MB MT4JSF6464HY-1G1
Xilinx XCF128X-FTG64C
Numonyx JS28F256P30T95
Xilinx XCCACE-TQ144I
(bottom of board)
USB JTAG download circuit
200 MHz OSC, oscillator socket, SMA
connectors
SiTime 200 MHz 2.5V LVDS OSC
MMD Components 66 MHz 2.5V
SMA pair
SMA pair
SMA x4
Card edge connector, 8-lane
AMP 136073-1
Marvell M88E1111 EPHY
Silicon Labs CP2103GM bridge
Cypress CY7C67300-100AXI
controller
Chrontel CH7301C-TF Video codec
ST Microelectronics M24C08-
WDW6TP
Right-angle link rate and direction
LEDs
Init (red), Done (green)
Status (green), Error (red)
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019
Table 1-1.
Schematic
Page
2 - 12
15
25
26
13
46
30
30
30
30
30
30
21
23
24
33
27
28, 29
32
13, 24, 31
24
31
13