Xilinx ML605 Hardware User's Manual page 2

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Revision History
The following table shows the revision history for this document.
Date Version
8/17/09 1.0
11/17/09 1.1
01/15/10 1.2
1/21/10 1.2.1
05/18/10 1.3
ML605 Hardware User Guide
Initial Xilinx release.
• Updated Figure 1-1, Figure
• Added Figure 1-7, Figure
• Updated Table 1-15 and
• Updated Appendix B, VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout
Appendix C, Xilinx Design
• Minor typographical edits.
• Updated Figure 1-2, Figure
and Table A-35. Miscellaneous typographical edits.
• Corrected typos in Table 1-31
Updated 7. Clock Generation, including
in Table 1-8. Updated Figure
to 19. VITA 57.1 FMC HPC Connector
respectively. Updated description of PMBus Pod and TI Fusion Digital Power Software
GUI in Onboard Power Regulation. Updated
LPC (J63) and HPC (J64) Connector
www.xilinx.com
Revision
1-2, Figure 1-3, Figure 1-11, and
1-8, Figure 1-10, and Figure
Table 1-18.
Constraints.
1-3, Figure 1-17, Table 1-3,
and Figure 1-28.
Table 1-7. Updated Package Placement column
1-17. Added notes about FMC HPC J64 and J63 connectors
and 20. VITA 57.1 FMC LPC
Table A-35,
Pinout, and Appendix C, Xilinx Design
Figure 1-14.
1-13.
Table 1-8, Table 1-9, Table A-34,
Connector,
Appendix B, VITA 57.1 FMC
Constraints.
UG534 (v1.9) February 26, 2019
and