Xilinx ML605 Hardware User's Manual page 61

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Note:
at 2.5V (non-adjustable). The 2.5V rail cannot be turned off. The ML605 VITA 57.1 FMC interfaces
are compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.
Table 1-28
Appendix B, VITA 57.1 FMC LPC (J63) and HPC (J64) Connector
Any signal named FMC_HPC_xxxx that is wired between a U1 FPGA pin and some other
device does not appear in this table.
Table 1-28: VITA 57.1 FMC HPC Connections
J64 FMC
Schematic Net Name
HPC Pin
A2 FMC_HPC_DP1_M2C_P
A3 FMC_HPC_DP1_M2C_N
A6 FMC_HPC_DP2_M2C_P
A7 FMC_HPC_DP2_M2C_N
A10 FMC_HPC_DP3_M2C_P
A11 FMC_HPC_DP3_M2C_N
A14 FMC_HPC_DP4_M2C_P
A15 FMC_HPC_DP4_M2C_N
A18 FMC_HPC_DP5_M2C_P
A19 FMC_HPC_DP5_M2C_N
A22 FMC_HPC_DP1_C2M_P
A23 FMC_HPC_DP1_C2M_N
A26 FMC_HPC_DP2_C2M_P
A27 FMC_HPC_DP2_C2M_N
A30 FMC_HPC_DP3_C2M_P
A31 FMC_HPC_DP3_C2M_N
A34 FMC_HPC_DP4_C2M_P
A35 FMC_HPC_DP4_C2M_N
A38 FMC_HPC_DP5_C2M_P
A39 FMC_HPC_DP5_C2M_N
C2 FMC_HPC_DP0_C2M_P
C3 FMC_HPC_DP0_C2M_N
C6 FMC_HPC_DP0_M2C_P
C7 FMC_HPC_DP0_M2C_N
C10 FMC_HPC_LA06_P
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019
4 differential clocks
The ML605 board VADJ voltage for the FMC HPC and LPC connectors (J64 and J63) is fixed
shows the VITA 57.1 FMC HPC connections. The connector pinout is in
U1 FPGA
Pin
AE3
AE4
AF5
AF6
AG3
AG4
AJ3
AJ4
AL3
AL4
AD1
AD2
AF1
AF2
AH1
AH2
AK1
AK2
AM1
AM2
AB1
AB2
AC3
AC4
AG20
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J64 FMC
Schematic Net Name
HPC Pin
B12 FMC_HPC_DP7_M2C_P
B13 FMC_HPC_DP7_M2C_N
B16 FMC_HPC_DP6_M2C_P
B17 FMC_HPC_DP6_M2C_N
B20 FMC_HPC_GBTCLK1_M2C_P
B21 FMC_HPC_GBTCLK1_M2C_N
B32 FMC_HPC_DP7_C2M_P
B33 FMC_HPC_DP7_C2M_N
B36 FMC_HPC_DP6_C2M_P
B37 FMC_HPC_DP6_C2M_N
D4 FMC_HPC_GBTCLK0_M2C_P
D5 FMC_HPC_GBTCLK0_M2C_N
D8 FMC_HPC_LA01_CC_P
D9 FMC_HPC_LA01_CC_N
D11 FMC_HPC_LA05_P
Detailed Description
Pinout.
U1 FPGA
Pin
AP5
AP6
AM5
AM6
AK6
AK5
AP1
AP2
AN3
AN4
AD6
AD5
AK19
AL19
AG22
61
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