Dvi Codec - Xilinx ML605 Hardware User's Manual

Chapter 1: ML605 Evaluation Board

14. DVI Codec

The ML605 features a DVI connector (P3) to support an external video monitor. The DVI
circuitry utilizes a Chrontel CH7301C (U38) capable of 1600 X 1200 resolution with 24-bit
color. The video interface chip drives both the digital and analog signals to the DVI
connector. A DVI monitor can be connected to the board directly. A VGA monitor can also
be connected to the board using the supplied DVI-to-VGA adaptor. The Chrontel CH7301C
is controlled by way of the video IIC bus.
The DVI connector
monitor's configuration parameters. These parameters can be read by the FPGA using the
DVI IIC bus (see
Table 1-17: DVI Controller Connections
U1 FPGA Pin Schematic Net Name
44
Send Feedback
(Table 1-17) supports the IIC protocol to allow the board to read the
15. IIC Bus).
AJ19 DVI_D0
AH19 DVI_D1
AM17 DVI_D2
AM16 DVI_D3
AD17 DVI_D4
AE17 DVI_D5
AK18 DVI_D6
AK17 DVI_D7
AE18 DVI_D8
AF18 DVI_D9
AL16 DVI_D10
AK16 DVI_D11
AD16 DVI_DE
AN17 DVI_H
AP17 DVI_RESET_B_LS
AD15 DVI_V
AC17 DVI_XCLK_N
AC18 DVI_XCLK_P
No Connect DVI_GPIO0
No Connect DVI_GPIO1
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U38 Chrontel CH7301C
Pin Number Pin Name
63 D0
62 D1
61 D2
60 D3
59 D4
58 D5
55 D6
54 D7
53 D8
52 D9
51 D10
50 D11
2 DE
4 H
13 RESET_B
5 V
56 XCLK_N
57 XCLK_P
8 GPIO0
7 GPIO1
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019