Xilinx ML605 Hardware User's Manual page 20

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Chapter 1:
ML605 Evaluation Board
Table 1-4: DDR3 SODIMM Connections (Cont'd)
20
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U1 FPGA Pin
Schematic Net Name
D26
F26
B26
E26
C24
D25
D27
C25
C27
B28
D29
B27
G27
A28
E24
G25
F28
B31
H29
H28
B30
A30
E29
F29
E11
B11
E14
D19
B22
A26
A29
A31
E12
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DDR3_D40
DDR3_D41
DDR3_D42
DDR3_D43
DDR3_D44
DDR3_D45
DDR3_D46
DDR3_D47
DDR3_D48
DDR3_D49
DDR3_D50
DDR3_D51
DDR3_D52
DDR3_D53
DDR3_D54
DDR3_D55
DDR3_D56
DDR3_D57
DDR3_D58
DDR3_D59
DDR3_D60
DDR3_D61
DDR3_D62
DDR3_D63
DDR3_DM0
DDR3_DM1
DDR3_DM2
DDR3_DM3
DDR3_DM4
DDR3_DM5
DDR3_DM6
DDR3_DM7
DDR3_DQS0_N
J1 SODIMM
Pin Number
Pin Name
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
158
DQ46
160
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
10
DQS0_N
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019

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