Xilinx ML605 Hardware User's Manual page 64

Chapter 1: ML605 Evaluation Board
Table 1-28: VITA 57.1 FMC HPC Connections (Cont'd)
J64 FMC
Schematic Net Name
HPC Pin
J2 FMC_HPC_CLK3_M2C_P
J3 FMC_HPC_CLK3_M2C_N
J6 FMC_HPC_HA03_P
J7 FMC_HPC_HA03_N
J9 FMC_HPC_HA07_P
J10 FMC_HPC_HA07_N
J12 FMC_HPC_HA11_P
J13 FMC_HPC_HA11_N
J15 FMC_HPC_HA14_P
J16 FMC_HPC_HA14_N
J18 FMC_HPC_HA18_P
J19 FMC_HPC_HA18_N
J21 FMC_HPC_HA22_P
J22 FMC_HPC_HA22_N
J24 FMC_HPC_HB01_P
J25 FMC_HPC_HB01_N
J27 FMC_HPC_HB07_P
J28 FMC_HPC_HB07_N
J30 FMC_HPC_HB11_P
J31 FMC_HPC_HB11_N
J33 FMC_HPC_HB15_P
J34 FMC_HPC_HB15_N
J36 FMC_HPC_HB18_P
J37 FMC_HPC_HB18_N
Notes:
1. Signals ending with _LS are not directly connected to the FMC HPC connector. _LS signals are connected between the listed U1
FPGA pin and a level shifter device. The signal connected between the shifted side of said device and the FMC HPC pin listed has
the same signal name, without the _LS on the end.
2. These signals do not connect to U1 FPGA pins. The pin numbers in the right-hand column identify the device and pin these signals
are connected to (U88.17 = U88 pin 17, and so on).
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U1 FPGA J64 FMC
Pin HPC Pin
H38
(2)
U84.6 K4
(2)
U84.7 K5
AA25 K7
Y26 K8
AA26 K10
AB26 K11
AG33 K13
AG32 K14
AA30 K16
AA31 K17
T33 K19
T34 K20
U28 K22
V29 K23
AN32 K25
AM32 K26
AJ34 K28
AH34 K29
AJ29 K31
AJ30 K32
AE28 K34
AE29 K35
AD25 K37
AD26 K38
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Schematic Net Name
FMC_HPC_LA32_N
(2)
FMC_HPC_CLK2_M2C_P
(2)
FMC_HPC_CLK2_M2C_N
FMC_HPC_HA02_P
FMC_HPC_HA02_N
FMC_HPC_HA06_P
FMC_HPC_HA06_N
FMC_HPC_HA10_P
FMC_HPC_HA10_N
FMC_HPC_HA17_CC_P
FMC_HPC_HA17_CC_N
FMC_HPC_HA21_P
FMC_HPC_HA21_N
FMC_HPC_HA23_P
FMC_HPC_HA23_N
FMC_HPC_HB00_CC_P
FMC_HPC_HB00_CC_N
FMC_HPC_HB06_CC_P
FMC_HPC_HB06_CC_N
FMC_HPC_HB10_P
FMC_HPC_HB10_N
FMC_HPC_HB14_P
FMC_HPC_HB14_N
FMC_HPC_HB17_CC_P
FMC_HPC_HB17_CC_N
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019
U1 FPGA
Pin
AG26
U83.6
U83.7
AB25
AC25
AA28
AA29
AD34
AC34
V30
W30
U31
U30
U26
U27
AF30
AG30
AF26
AE26
AF28
AF29
AE27
AD27
AG27
AG28