Xilinx ML605 Hardware User's Manual page 33

GTX SMA Clock
The ML605 includes a pair of SMA connectors for a GTX (MGT) Clock as described in
Figure 1-9
X-Ref Target - Figure 1-9
SMA_REFCLK_N
SMA_REFCLK_P
Table 1-7: ML605 Clock Connections
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019
and Table 1-7.
Figure 1-9: GTX SMA Clock
U1 FPGA Pin Schematic Net Name
H9 SYSCLK_N
J9 SYSCLK_P
U23 USER_CLOCK
F5 SMA_REFCLK_N
F6 SMA_REFCLK_P
M22 USER_SMA_CLOCK_N
L23 USER_SMA_CLOCK_P
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J30 32K10K-400E3
SMA_REFCLK_C_N1
SIG
J31 32K10K-400E3
SMA_REFCLK_C_P1
SIG
SMA Pin
U11.5
U11.4
X5.5
J30.1
J31.1
J55.1
J58.1
Detailed Description
2
GND1
3
GND2
4
GND3
5
GND4
6
GND5
7
GND6
8
GND7
2
GND1
3
GND2
4
GND3
5
GND4
6
GND5
7
GND6
8
GND7
UG534_09_081309
33
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