100/1000 Tri-Speed Ethernet Phy - Xilinx ML605 Hardware User's Manual

Table 1-10: SFP Module Connections
Notes:
1. The SFP TX Disable pin 3 is driven by transistor Q22, the base of which is driven

11. 10/100/1000 Tri-Speed Ethernet PHY

The ML605 utilizes the onboard Marvell Alaska PHY device (88E1111) for Ethernet
communications at 10, 100, or 1000 Mb/s. The board supports MII, GMII, RGMII, and
SGMII interfaces from the FPGA to the PHY
provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector with built-in
magnetics.
Table 1-11: PHY Default Interface Mode
On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY
address 0b00111 using the settings shown in
via software commands passed over the MDIO interface.
Table 1-12: Board Connections for PHY Configuration Pins
CFG0
CFG1
CFG2
CFG3
CFG4
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019
U1 FPGA Pin Schematic Net Name
E3
E4
C3
C4
V23
AP12 SFP_TX_DISABLE
by the FPGA signal SFP_TX_DISABLE_FPGA.
Mode
GMII/MII to copper
Jumper over pins 1-2
(default)
SGMII to copper,
Jumper over pins 2-3
no clock
RGMII Jumper over pins 1-2
Connection on
Pin
Board Definition and Value
V 2.5V PHYADR[2] = 1
CC
Ground ENA_PAUSE = 0
V 2.5V
CC
V 2.5V
CC
V 2.5V HWCFG_MD[2] = 1
CC
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SFP_RX_P
SFP_RX_N
SFP_TX_P
SFP_TX_N
SFP_LOS
(1)
(Table 1-11). The PHY connection to a user-
Jumper Settings
J66
Jumper over pins 1-2
Jumper over pins 2-3
No jumper
Table 1-12. These settings can be overwritten
Bit[2] Bit[1]
Definition and Value
PHYADR[1] = 1
PHYADR[4] = 0
ANEG[3] = 1 ANEG[2] = 1
ANEG[0] = 1 ENA_XC = 1
HWCFG_MD[1] = 1
Detailed Description
P4 SFP Module Connector
Pin Number Pin Name
13 RDP_13
12 RDN_12
18 TDP_18
19 TDN_19
8 LOS
3 TX_DISABLE
J67 J68
No jumper
No jumper
Jumper on
Bit[0]
Definition and Value
PHYADR[0] = 1
PHYADR[3] = 0
ANEG[1] = 1
DIS_125 = 1
HWCFG_MD[0] = 1
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