Xilinx ML605 Hardware User's Manual page 21

Table 1-4: DDR3 SODIMM Connections (Cont'd)
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019
U1 FPGA Pin Schematic Net Name
D12
J12
H12
A14
A13
H20
H19
C23
B23
A25
B25
G28
H27
D30
C30
F18
E17
E18 DDR3_RESET_B
K18
K17
D17 DDR3_TEMP_EVENT
B17
C17
L19
M18
M17
H18
G18
L16
K16
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DDR3_DQS0_P
DDR3_DQS1_N
DDR3_DQS1_P
DDR3_DQS2_N
DDR3_DQS2_P
DDR3_DQS3_N
DDR3_DQS3_P
DDR3_DQS4_N
DDR3_DQS4_P
DDR3_DQS5_N
DDR3_DQS5_P
DDR3_DQS6_N
DDR3_DQS6_P
DDR3_DQS7_N
DDR3_DQS7_P
DDR3_ODT0
DDR3_ODT1
DDR3_S0_B
DDR3_S1_B
DDR3_WE_B
DDR3_CAS_B
DDR3_RAS_B
DDR3_CKE0
DDR3_CKE1
DDR3_CLK0_N
DDR3_CLK0_P
DDR3_CLK1_N
DDR3_CLK1_P
Detailed Description
J1 SODIMM
Pin Number Pin Name
12 DQS0_P
27 DQS1_N
29 DQS1_P
45 DQS2_N
47 DQS2_P
62 DQS3_N
64 DQS3_P
135 DQS4_N
137 DQS4_P
152 DQS5_N
154 DQS5_P
169 DQS6_N
171 DQS6_P
186 DQS7_N
188 DQS7_P
116 ODT0
120 ODT1
30 RESET_B
114 S0_B
121 S1_B
198 EVENT_B
113 WE_B
115 CAS_B
110 RAS_B
73 CKE0
74 CKE1
103 CK0_N
101 CK0_P
104 CK1_N
102 CK1_P
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