Xilinx ML605 Hardware User's Manual
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Xilinx ML605 Hardware User's Manual

Xilinx ML605 Hardware User's Manual

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ML605 Hardware
User Guide
UG534 (v1.9) February 26, 2019

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  • Page 1 ML605 Hardware User Guide UG534 (v1.9) February 26, 2019...
  • Page 2 (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
  • Page 3 Updated Figure 1-2. Added Regulatory and Compliance Information. 02/26/19 Updated Appendix C, Xilinx Design Constraints, Appendix D, Regulatory and Compliance Information, and the 2. 512 MB DDR3 Memory SODIMM section. UG534 (v1.9) February 26, 2019 www.xilinx.com ML605 Hardware User Guide...
  • Page 4 ML605 Hardware User Guide www.xilinx.com UG534 (v1.9) February 26, 2019...

  • Page 5: Table Of Contents

    ..........8 Chapter 1: ML605 Evaluation Board Overview .
  • Page 6 Appendix A: Default Switch and Jumper Settings Appendix B: VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout Appendix C: Xilinx Design Constraints Overview ..............83...

  • Page 7: Preface: About This Guide

    Guide Contents This manual contains the following chapters: • Chapter 1, ML605 Evaluation Board, provides an overview of the embedded development board and details the components and features of the ML605 board. • Appendix A, Default Switch and Jumper Settings. •...

  • Page 8: Additional Support Resources

    PCB and interface level. Additional Support Resources To search the database of silicon and software questions and answers or to create a technical support request in the Request Portal, see the Xilinx website at: www.xilinx.com/support www.xilinx.com...

  • Page 9: Chapter 1: Ml605 Evaluation Board

    Chapter 1 ML605 Evaluation Board Overview The ML605 board enables hardware and software developers to create or evaluate designs targeting the Virtex®-6 XC6VLX240T-1FFG1156 FPGA. The ML605 provides board features common to many embedded processing systems. Some commonly used features include: a DDR3 SODIMM memory, an 8-lane PCI Express®...

  • Page 10: Features

    Chapter 1: ML605 Evaluation Board Features The ML605 provides the following features: • 1. Virtex-6 XC6VLX240T-1FFG1156 FPGA • 2. 512 MB DDR3 Memory SODIMM • 3. 128 Mb Platform Flash XL • 4. 32 MB Linear BPI Flash • 5. System ACE CF and CompactFlash Connector •...
  • Page 11 Configuration Options • 3. 128 Mb Platform Flash XL • 4. 32 MB Linear BPI Flash • 5. System ACE CF and CompactFlash Connector • 6. USB JTAG ML605 Hardware User Guide www.xilinx.com Send Feedback UG534 (v1.9) February 26, 2019...

  • Page 12: Block Diagram

    UG534_01_092709 Figure 1-1: ML605 High-Level Block Diagram Related Xilinx Documents Prior to using the ML605 Evaluation Board, users should be familiar with Xilinx resources. Appendix E, References for a direct link to Xilinx documentation. See the following locations for additional documentation on Xilinx tools and solutions: •...

  • Page 13: Electrostatic Discharge Caution

    Put the adapter down only on an anti-static surface such as the bag supplied in your kit. • If you are returning the adapter to Xilinx Product Support, place it back in its anti- static bag immediately. Detailed Description Figure 1-2...
  • Page 14 Chapter 1: ML605 Evaluation Board The numbered features in Figure 1-2 correlate to the features and notes listed in Table 1-1. Table 1-1: ML605 Features Schematic Number Feature Notes Page Virtex-6 FPGA XC6VLX240T-1FFG1156 2 - 12 DDR3 SODIMM Micron 512 MB MT4JSF6464HY-1G1...
  • Page 15 Detailed Description Table 1-1: ML605 Features (Cont’d) Schematic Number Feature Notes Page User I/O a. User LEDs, green (8) User I/O (active-High) 30, 31, 33 b. User pushbuttons, N.O. User I/O (active-High) momentary (5) c. User LEDs, green (5) User I/O (active-High) d.

  • Page 16: Virtex-6 Xc6Vlx240T-1Ffg1156 Fpga

    JTAG (using the included USB-A to Mini-B cable) • JTAG (using System ACE CF and CompactFlash card) The ML605 supports Master BPI-Up, JTAG, and Slave SelectMAP. These are selected by setting M[2:0] options 010, 101 and 110 shown in Table 1-2.

  • Page 17: I/O Voltage Rails

    Xilinx Virtex-6 FPGA documentation for more information. 2. 512 MB DDR3 Memory SODIMM The ML605 204-pin 1.5V SODIMM socket J1 supports up to 2 GB SODIMMs. The ML605 is delivered with a 512 MB DDR3 SODIMM for user applications. •...
  • Page 18 Chapter 1: ML605 Evaluation Board The ML605 XC6SVX240T FPGA DDR memory interface performance is documented in the Virtex-6 FPGA Data Sheet: DC and Switching Characteristics (DS152) [Ref The ML605 DDR3 64-bit wide interface has been tested to 800 MT/s. The DDR3 interface is implemented in FPGA banks 25, 26, 35, and 36. DCI VRP/N resistor connections are only implemented banks 26 and 36.
  • Page 19 DDR3_D26 DQ26 DDR3_D27 DQ27 DDR3_D28 DQ28 DDR3_D29 DQ29 DDR3_D30 DQ30 DDR3_D31 DQ31 DDR3_D32 DQ32 DDR3_D33 DQ33 DDR3_D34 DQ34 DDR3_D35 DQ35 DDR3_D36 DQ36 DDR3_D37 DQ37 DDR3_D38 DQ38 DDR3_D39 DQ39 ML605 Hardware User Guide www.xilinx.com Send Feedback UG534 (v1.9) February 26, 2019...
  • Page 20 DDR3_D55 DQ55 DDR3_D56 DQ56 DDR3_D57 DQ57 DDR3_D58 DQ58 DDR3_D59 DQ59 DDR3_D60 DQ60 DDR3_D61 DQ61 DDR3_D62 DQ62 DDR3_D63 DQ63 DDR3_DM0 DDR3_DM1 DDR3_DM2 DDR3_DM3 DDR3_DM4 DDR3_DM5 DDR3_DM6 DDR3_DM7 DDR3_DQS0_N DQS0_N www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...
  • Page 21 DDR3_ODT1 ODT1 DDR3_RESET_B RESET_B DDR3_S0_B S0_B DDR3_S1_B S1_B DDR3_TEMP_EVENT EVENT_B DDR3_WE_B WE_B DDR3_CAS_B CAS_B DDR3_RAS_B RAS_B DDR3_CKE0 CKE0 DDR3_CKE1 CKE1 DDR3_CLK0_N CK0_N DDR3_CLK0_P CK0_P DDR3_CLK1_N CK1_N DDR3_CLK1_P CK1_P ML605 Hardware User Guide www.xilinx.com Send Feedback UG534 (v1.9) February 26, 2019...

  • Page 22: Mb Platform Flash Xl

    FPGA design recommendations. 4. 32 MB Linear BPI Flash A Numonyx JS28F256P30 Linear BPI Flash memory (P30) on the ML605 provides 32 MB of non-volatile storage that can be used for configuration as well as software storage. The Linear BPI Flash shares the dual use configuration pins in parallel with the XCF128 Platform Flash XL.

  • Page 23: Ml605 Flash Boot Options

    UG534_03_011110 Figure 1-3: Platform Flash and BPI Flash Block Diagram ML605 Flash Boot Options The ML605 has two parallel wired flash memory devices as shown in Figure 1-3. At ML605 power-up, before FPGA configuration, DIP switch S2 switch 2 selects which flash device, U4 (BPI) or U27 (Platform Flash), provides the boot bitstream.
  • Page 24 DQ03 FLASH_D4 DQ04 FLASH_D5 DQ05 FLASH_D6 DQ06 FLASH_D7 DQ07 FLASH_D8 DQ08 FLASH_D9 DQ09 FLASH_D10 DQ10 DQ10 FLASH_D11 DQ11 DQ11 FLASH_D12 DQ12 DQ12 FLASH_D13 DQ13 DQ13 FLASH_D14 DQ14 DQ14 www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...
  • Page 25 2. FPGA control flash memory select signal connected to pin U10.3 3. Platform Flash select signal connected to pin U10.6 4. BPI Flash select signal connected to pin U10.4 ML605 Hardware User Guide www.xilinx.com Send Feedback UG534 (v1.9) February 26, 2019...
  • Page 26 Resources tab for more information. Also, see the Platform Flash XL High-Density Configuration and Storage Device Data Sheet (DS617) [Ref 17] and the Virtex-6 Configuration User Guide (UG360) [Ref 10]. www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...

  • Page 27: System Ace Cf And Compactflash Connector

    CompactFlash, with the xilinx.sys file located in the root directory. The xilinx.sys file is used by the System ACE CF controller to define the project directory structure, which consists of one main folder containing eight sub-folders used to store the eight ACE files containing the configuration images.
  • Page 28 1. The System ACE CF clock is sourced from U28 33.000 MHz osc. See the System ACE CF product page, System ACE file generation information, and the and the System ACE CompactFlash Solution Data Sheet (DS080). [Ref 18] www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...

  • Page 29: Usb Jtag

    6. USB JTAG JTAG configuration is provided through onboard USB-to-JTAG configuration logic where a computer host accesses the ML605 JTAG chain through a Type-A (computer host side) to Type-Mini-B (ML605 side) USB cable. The JTAG chain of the board is illustrated in the figure below. JTAG configuration is allowable at any time under any mode pin setting.

  • Page 30: Clock Generation

    There are three FPGA fabric clock sources available on the ML605 (refer to Table 1-7). Oscillator (Differential) The ML605 has one 2.5V LVDS differential 200 MHz oscillator (U11) soldered onto the board and wired to an FPGA global clock input. The 200 MHz signal names are SYSCLK_N and SYSCLK_P. •...
  • Page 31 Detailed Description X-Ref Target - Figure 1-7 Silkscreened outline has beveled corner Socket has notch in crossbar UG534_07_092109 Figure 1-7: ML605 Oscillator Socket Pin 1 Location Identifiers ML605 Hardware User Guide www.xilinx.com Send Feedback UG534 (v1.9) February 26, 2019...

  • Page 32: Sma Connectors (Differential)

    Oscillator top has corner dot marking UG534_08_092109 Figure 1-8: ML605 Oscillator Pin 1 Location Identifiers SMA Connectors (Differential) A high-precision clock signal can be provided to the FPGA using differential clock signals through the onboard 50Ω SMA connectors J58(P)/J55(N). This differential user clock has the signal names USER_SMA_CLOCK_N and USER_SMA_CLOCK_P.
  • Page 33 Detailed Description GTX SMA Clock The ML605 includes a pair of SMA connectors for a GTX (MGT) Clock as described in Figure 1-9 Table 1-7. X-Ref Target - Figure 1-9 J30 32K10K-400E3 GND1 GND2 GND3 SMA_REFCLK_C_N1 GND4 GND5 GND6 GND7...

  • Page 34: Multi-Gigabit Transceivers (Gtx Mgts)

    Chapter 1: ML605 Evaluation Board 8. Multi-Gigabit Transceivers (GTX MGTs) The ML605 provides access to 20 MGTs. • Eight (8) of the MGTs are wired to the PCIe x8 Endpoint (P1) edge connector fingers • Eight (8) of the MGTs are wired to the FMC HPC connector (J64) •...

  • Page 35: Pci Express Endpoint Connectivity

    The ML605 board trace impedance on all PCIe lanes supports both Gen1 and Gen2 applications. The ML605 supports up to Gen1 x8 and Gen2 x4 as shipped with a -1 speed grade for the LX240T device.
  • Page 36 Integrated Endpoint block GTXE1_X0Y11 receive pair PCIE_RX4_N PETn4 PCIE_RX5_P PETp5 Integrated Endpoint block GTXE1_X0Y10 receive pair PCIE_RX5_N PETn5 PCIE_RX6_P PETp6 Integrated Endpoint block GTXE1_X0Y9 receive pair PCIE_RX6_N PETn6 www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...
  • Page 37 AC adapter might be required. If a different AC adapter is used, its load regulation should be better than ±10%. ML605 power switch SW2 turns the board on and off by controlling the 12V supply to the board.

  • Page 38: Sfp Module Connector

    Jumper J54 SFP_RT_SEL Jumper Pins 1-2 = Full Bandwidth Jumper Pins 2-3 = Reduced Bandwidth Test Point J51 SFP_LOS High = Loss of Receiver Signal Low = Normal Operation www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...

  • Page 39: 100/1000 Tri-Speed Ethernet Phy

    FPGA signal SFP_TX_DISABLE_FPGA. 11. 10/100/1000 Tri-Speed Ethernet PHY The ML605 utilizes the onboard Marvell Alaska PHY device (88E1111) for Ethernet communications at 10, 100, or 1000 Mb/s. The board supports MII, GMII, RGMII, and SGMII interfaces from the FPGA to the PHY (Table 1-11).

  • Page 40: Sgmii Gtx Transceiver Clock Generation

    AH13 PHY_RESET RESET_B AL13 PHY_CRS AK13 PHY_COL AP11 PHY_RXCLK RXCLK AG12 PHY_RXER RXER AM13 PHY_RXCTL_RXDV RXDV AN13 PHY_RXD0 RXD0 AF14 PHY_RXD1 RXD1 AE14 PHY_RXD2 RXD2 AN12 PHY_RXD3 RXD3 www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...
  • Page 41 SOUT_N See the Marvell Alaska Gigabit Ethernet Transceivers product page for more information. [Ref 31] Also, see the LogiCORE™ IP Tri-Mode Ethernet MAC User Guide (UG138). [Ref 19] ML605 Hardware User Guide www.xilinx.com Send Feedback UG534 (v1.9) February 26, 2019...

  • Page 42: Usb-To-Uart Bridge

    The ML605 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U34) which allows connection to a host computer with a USB cable. The USB cable is supplied in this evaluation kit (Type A end to host computer, Type Mini-B end to ML605 connector J21). Table 1-14 details the ML605 J21 pinout.

  • Page 43: Usb Controller

    Detailed Description 13. USB Controller The ML605 provides USB support via a Cypress CY7C67300 EZ-Host™ Programmable Embedded USB Host and Peripheral Controller (U81). The host port is a USB Type-A connector (J5). A USB keyboard (without an internal USB hub) will be able to connect to this USB Host port to demonstrate functionality.

  • Page 44: Dvi Codec

    ML605 Evaluation Board 14. DVI Codec The ML605 features a DVI connector (P3) to support an external video monitor. The DVI circuitry utilizes a Chrontel CH7301C (U38) capable of 1600 X 1200 resolution with 24-bit color. The video interface chip drives both the digital and analog signals to the DVI connector.

  • Page 45: Iic Bus

    Detailed Description 15. IIC Bus The ML605 implements four IIC bus interfaces at the FPGA. The "MAIN" IIC bus hosts four items: • FPGA U1 Bank 34 "MAIN" IIC interface • 8Kb NV Memory U6 • FMC HPC connector J64 •...
  • Page 46 2 Kb EEPROM IIC_SDA_MAIN Addr: 0b1010000 Addr: 0b0011011 Temperature Sensor DVI CODEC SFP_MOD_DEF2 SFP MODULE CHRONTEL CONNECTOR SFP_MOD_DEF1 CH730C-TF Addr: 0b1010000 Addr: 0b1110110 UG534_14_092109 Figure 1-14: IIC Bus Topology www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...

  • Page 47: Kb Nv Memory

    Detailed Description 8 Kb NV Memory The ML605 hosts an 8 Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage memory device (U6). The IIC address of U7 is 0b1010100, and U6 is not write protected (WP pin 7 is tied to GND).

  • Page 48: Status Leds

    DDR3 VTTDDR Power Good DS30 SYSACE_ERR_LED System ACE CF System ACE CF Error Error LED DS31 FPGA_INIT_B INIT FPGA Initialization in progress DS32 DVI_GPIO1_FMC_C2M_PG GREEN FMC PWR GD FMC Power Good www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...

  • Page 49: Ethernet Phy Status Leds

    Detailed Description Ethernet PHY Status LEDs The Ethernet PHY status LEDs are mounted to be visible when the ML605 board is installed into a PC motherboard. They are mounted in right-angle, plastic housings and can be seen on the connector end of the board. This cluster of six LEDs is installed adjacent to the RJ45 Ethernet jack P2.

  • Page 50: Fpga Init And Done Leds

    Chapter 1: ML605 Evaluation Board FPGA INIT and DONE LEDs The typical Xilinx FPGA power up and configuration status LEDs are present on the ML605. The red INIT LED DS31 comes on momentarily after the FPGA powers up and during its internal power-on process.

  • Page 51: User Leds

    Detailed Description User LEDs The ML605 provides two groups of active-High LEDs as described in Figure 1-18 Table 1-21. X-Ref Target - Figure 1-18 GPIO_LED_0 GPIO_LED_1 GPIO_LED_2 GPIO_LED_3 GPIO_LED_4 GPIO_LED_5 GPIO_LED_6 GPIO_LED_7 H-1X8 27.4 27.4 27.4 27.4 27.4 27.4 27.4 27.4...

  • Page 52: User Pushbutton Switches

    AH27 GPIO_LED_N – DS20 User Pushbutton Switches The ML605 provides six active-High pushbutton switches: • SW5, SW6, SW7, SW8 and SW9, arranged in a diamond configuration to depict “directional” headings North, South, East, West and Center respectively • SW10 CPU Reset pushbutton...

  • Page 53: User Dip Switch

    SW7.2 GPIO_SW_W SW8.2 GPIO_SW_C SW9.2 CPU_RESET SW10.2 User DIP Switch The ML605 includes an active-High eight pole DIP switch as described in Figure 1-20 Table 1-23. X-Ref Target - Figure 1-20 VCC1V5 GPIO DIP SW1 GPIO DIP SW2 GPIO DIP SW3...

  • Page 54: User Sma Gpio

    Chapter 1: ML605 Evaluation Board User SMA GPIO The ML605 includes an pair of SMA connectors for GPIO as described in Figure 1-21 Table 1-24. X-Ref Target - Figure 1-21 J56 32K10K-400E3 GND1 GND2 GND3 GND4 GND5 GND6 GND7 USER SMA GPIO N...

  • Page 55: Lcd Display (16 Character X 2 Lines)

    Detailed Description LCD Display (16 Character x 2 Lines) The ML605 board has a 16-character x 2-line LCD (Display Tech S162D BA BC, installed onto J41 2x7 header) on the board to display text information. Potentiometer R270 adjusts the contrast of the LCD. A ST2378E (U33) 2.5V-to-5V level-shifter is used to shift the voltage level between the FPGA and the LCD.

  • Page 56: Switches

    MODE, Boot EEPROM Select and CCLK Osc Enable DIP switch S2 (active-High) Power On/Off Slide Switch SW2 SW2 is the ML605 board main power on/off switch. Sliding the switch actuator from the off to on position applies 12V power from either J60 (6-pin Mini-Fit) or J25 (4-pin ATX) Ω...

  • Page 57: Fpga_Prog_B Pushbutton Sw4 (Active-Low)

    5. System ACE CF and CompactFlash Connector for more details. X-Ref Target - Figure 1-25 silkscreen: “SYSACE RESET” SYSACE_RESET_B Pushbutton UG534_25_073109 Figure 1-25: System ACE CF RESET_B Pushbutton SW3 ML605 Hardware User Guide www.xilinx.com Send Feedback UG534 (v1.9) February 26, 2019...

  • Page 58: System Ace Cf Compactflash Image Select Dip Switch S1

    S1 switch 4 is the System ACE controller enable switch. When ON, this switch allows the System ACE to boot at power-on if it finds a CF card present. In order to boot from BPI Flash U4 or Xilinx Platform Flash (U27) without System ACE contention, S1 switch 4 must be OFF. www.xilinx.com...

  • Page 59: Mode, Osc Enable, Boot Eeprom Select, And Addr Select Dip Switch S2

    SiT8102 (X4). When switch 1 is closed (CCLK_EXTERNAL High), X4 drives a 47 MHz clock onto the FPGA_CCLK signal. Boot EEPROM Select: S2 switch 2 is used to select the between the Xilinx Platform Flash or the Numonyx Linear BPI Flash for the FPGA boot memory device.

  • Page 60: Vita 57.1 Fmc Hpc Connector

    4. 32 MB Linear BPI Flash for details. 19. VITA 57.1 FMC HPC Connector The ML605 implements both the High Pin Count (HPC, J64) and Low Pin Count (LPC, J63) connector options of VITA 57.1.1 FMC specification. This section discusses the FMC HPC J64 connector.
  • Page 61 4 differential clocks Note: The ML605 board VADJ voltage for the FMC HPC and LPC connectors (J64 and J63) is fixed at 2.5V (non-adjustable). The 2.5V rail cannot be turned off. The ML605 VITA 57.1 FMC interfaces are compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.
  • Page 62 FMC_HPC_HA16_P AC33 FMC_HPC_HA12_N AE32 FMC_HPC_HA16_N AB33 FMC_HPC_HA15_P AB32 FMC_HPC_HA20_P FMC_HPC_HA15_N AC32 FMC_HPC_HA20_N FMC_HPC_HA19_P FMC_HPC_HB03_P AL30 FMC_HPC_HA19_N FMC_HPC_HB03_N AM31 FMC_HPC_HB02_P AP32 FMC_HPC_HB05_P AN33 FMC_HPC_HB02_N AP33 FMC_HPC_HB05_N AN34 FMC_HPC_HB04_P AM33 www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...
  • Page 63 FMC_HPC_LA25_N AM28 FMC_HPC_LA24_P AN30 FMC_HPC_LA29_P AL28 FMC_HPC_LA24_N AM30 FMC_HPC_LA29_N AK28 FMC_HPC_LA28_P AK27 FMC_HPC_LA31_P AL29 FMC_HPC_LA28_N AJ27 FMC_HPC_LA31_N AK29 FMC_HPC_LA30_P AJ24 FMC_HPC_LA33_P AH23 FMC_HPC_LA30_N AK24 FMC_HPC_LA33_N AH24 FMC_HPC_LA32_P AG25 ML605 Hardware User Guide www.xilinx.com Send Feedback UG534 (v1.9) February 26, 2019...
  • Page 64 2. These signals do not connect to U1 FPGA pins. The pin numbers in the right-hand column identify the device and pin these signals are connected to (U88.17 = U88 pin 17, and so on). www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...
  • Page 65 10 uF VREF_B_M2C 0-VIO_B_M2C 1 mA +/- 2% 10 uF 3P3VAUX 3.3V 20 mA +/- 5% 150 uF 3P3V 3.3V +/- 5% 1000 uF 12P0V +/- 5% 1000 uF ML605 Hardware User Guide www.xilinx.com Send Feedback UG534 (v1.9) February 26, 2019...

  • Page 66: Vita 57.1 Fmc Lpc Connector

    -3 dB insertion loss point within a two-level signaling environment. Note: The ML605 board VADJ voltage for the FMC HPC and LPC connectors (J64 and J63) is fixed at 2.5V (non-adjustable). The 2.5V rail cannot be turned off. The ML605 VITA 57.1 FMC interfaces are compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.
  • Page 67 FMC_LPC_LA27_N FMC_LPC_LA23_N FMC_LPC_LA26_P FMC_LPC_LA26_N FMC_LPC_CLK1_M2C_P FMC_LPC_PRSNT_M2C_L FMC_LPC_CLK1_M2C_N FMC_LPC_CLK0_M2C_P FMC_LPC_LA00_CC_P FMC_LPC_CLK0_M2C_N FMC_LPC_LA00_CC_N FMC_LPC_LA02_P FMC_LPC_LA03_P FMC_LPC_LA02_N FMC_LPC_LA03_N FMC_LPC_LA04_P FMC_LPC_LA08_P FMC_LPC_LA04_N FMC_LPC_LA08_N FMC_LPC_LA07_P FMC_LPC_LA12_P FMC_LPC_LA07_N FMC_LPC_LA12_N FMC_LPC_LA11_P FMC_LPC_LA16_P FMC_LPC_LA11_N FMC_LPC_LA16_N FMC_LPC_LA15_P ML605 Hardware User Guide www.xilinx.com Send Feedback UG534 (v1.9) February 26, 2019...

  • Page 68: Power Management

    Mini-Fit type connector J60. The AC-to-DC power supply included in the kit has a mating 6-pin plug. When the ML605 is installed into a table top or tower PC's PCIe slot, the ML605 is typically powered from the PC ATX power supply. One of the ATX hard disk type 4-pin power connectors is plugged into ML605 connector J25.

  • Page 69: Onboard Power Regulation

    Detailed Description Onboard Power Regulation Figure 1-28 shows the ML605 onboard power supply architecture. The ML605 uses power solutions from Texas Instruments. X-Ref Target - Figure 1-28 Power Supply PWR Jack J25/J60 Linear Regulator TL1963 VCC5 5.0V@1.5A max Power Controller 1...
  • Page 70 _AVCC Rail 1.25 1.156 1.125 1.375 _AVTT UCD9240 Shut Shut Shut 14.5 (Addr 53) down down down Rail VCC1V5 1.388 1.35 1.65 _FPGA Rail VCC3V3 3.052 2.97 3.63 www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...
  • Page 71 UCD92xx series of controllers from a Windows- based host computer via the PMBus pod. The ML605 onboard connector J3 is wired for the TI EVM interface and provides access to the PMBUS and UCD9240s for monitoring purposes.

  • Page 72: System Monitor

    -40°C to +125°C is obtained using an external reference. Figure 1-29 illustrates the power supply and reference options on the ML605. For a more detailed discussion of these requirements, see the Virtex-6 FPGA System Monitor User Guide (UG370).
  • Page 73 C169 AGND SYSMON_VP 0.01UF To Measure VCCINT Current: Dedicated Analog Inputs Jumper on 9-11, 10-12 Connect Vccint shunt to Vp,Vn UG534_37 _081209 Figure 1-30: System Monitor Header (J35) ML605 Hardware User Guide www.xilinx.com Send Feedback UG534 (v1.9) February 26, 2019...
  • Page 74 In addition to monitoring the FPGA core supply power consumption, two auxiliary analog input channels (of the 16 that are available) are used to implement a power monitor for the entire ML605 board. The board power is monitored at the 12V power input connector. Figure 1-31 shows how the power monitor is implemented and connected to the System Monitor auxiliary input channels 12 and 13.
  • Page 75 In highly demanding situations, active thermal management in the form of a heat sink and fan may be required. In order to support this, drive circuitry for an external fan has been provided on the ML605. A fan with tach output can be connect at header J59 as shown in Figure 1-32.
  • Page 76 System Monitor ML605 Demonstration Design The various features described in this section are easily evaluated using a MicroBlaze™ based reference designed provided with the ML605 Evaluation Board. This reference design supports a UART based interface using a terminal program such as Hyperterminal to provide information on the FPGA power supplies, temperature, and power consumption.

  • Page 77: Configuration Options

    BPI Mode JTAG With the mode set to JTAG 101, the ML605 will not attempt to boot or load a bitstream from either of the Flash devices. If a CompactFlash (CF) card is installed in the CF socket U73, System ACE CF will attempt to load a bitstream from the CF card image address pointed to by the image select switch S1.
  • Page 78 Chapter 1: ML605 Evaluation Board www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...
  • Page 79 1. S1 position 4 is the System ACE controller enable switch. When ON, this switch allows the System ACE to boot at power on if it finds a CF card present. In order to boot from BPI Flash or Xilinx Platform Flash without System ACE contention, S1 switch 4 must be OFF.

  • Page 80: Appendix A: Default Switch And Jumper Settings

    R-kelvin on VCCINT Jump 10 - 12 SFP Module: Full BW Jump 1 - 2 SFP Enable Jump 1 - 2 PCIe Lane Size: 1 lane Jump 1 - 2 www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...
  • Page 81 VADJ 3P3V V ADJ G ND 3P 3V Figure B-34: FMC LPC Connector Pinout For more information, refer to the VITA 57.1 FMC LPC Connections table (Table 1-30). ML605 Hardware User Guide www.xilinx.com Send Feedback UG534 (v1.9) February 26, 2019...
  • Page 82 FMC HPC connector. X-Ref Target - Figure B-35 Figure B-35: FMC HPC Connector Pinout For more information, refer to the VITA 57.1 FMC HPC Connections table (Table 1-28). www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...

  • Page 83: Appendix C: Xilinx Design Constraints

    Overview The Xilinx Design Constraints (UCF) file template provides for designs targeting the ML605 evaluation board. Net names in the constraints correlate with net names on the latest ML605 evaluation board schematic. Identify the appropriate pins and replace the net names with net names in the user RTL.
  • Page 84 Appendix C: Xilinx Design Constraints www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...

  • Page 85: Appendix D: Regulatory And Compliance Information

    Information This product is designed and tested to conform to the European Union directives and standards described in this section. See the Virtex-6 FPGA ML605 Evaluation Kit - Known Issues and Release Notes Xilinx Master Answer Record 34836 concerning the CE requirements for the PC Test Environment.

  • Page 86: Safety

    Xilinx has met its national obligations to the EU WEEE Directive by registering in those countries to which Xilinx is an importer. Xilinx has also elected to join WEEE Compliance Schemes in some countries to help manage customer returns at end-of-life.

  • Page 87: Appendix E: References

    This section provides references to documentation supporting Virtex-6 FPGAs, tools, and IP. For additional information, see www.xilinx.com/support/documentation/index.htm. Virtex-6 FPGA ML605 Evaluation Kit - Known Issues and Release Notes Xilinx Master Answer Record 34836. Xilinx Documents supporting the ML605 Evaluation Board:...
  • Page 88 SIG, PCI Express Specifications 31. Marvell, Alaska Gigabit Ethernet Transceivers Product Page Cypress Semiconductor, CY7C67300 Data Sheet USB Implementers Forum, Inc., USB Specifications Micro, M24C08 Data Sheet Samtec, Inc. www.xilinx.com ML605 Hardware User Guide Send Feedback UG534 (v1.9) February 26, 2019...

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