Appendix B: Xilinx Design Constraints; Overview - Xilinx SP701 User Manual

Xilinx Design Constraints

Overview

The Xilinx design constraints (XDC) file template for the SP701 board provides for designs
targeting the SP701 evaluation board. Net names in the constraints file correlate with net names
on the latest SP701 evaluation board schematic. Identify the appropriate pins and replace the net
names with net names in the user RTL. See the Vivado Design Suite User Guide: Using Constraints
(UG903) for more information.
The FMC LPC connector J21 is connected to FPGA banks powered by the variable voltage V
(1.8V nominal). Because different FMC cards implement different circuitry, the FMC bank I/O
standards must be uniquely defined by each customer.
IMPORTANT! See the
UG1319 (v1.0) July 12, 2019
SP701 Board User Guide
SP701 board website documentation tab
Appendix B
(Board Files check box) for the XDC file.
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