Appendix C: Xilinx Design Constraints; Overview - Xilinx SP605 Hardware User's Manual
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Also See for SP605:
- User manual (67 pages) ,
- Hardware setup manual (2 pages) ,
- Hardware tutorial (40 pages)
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Xilinx Design Constraints
Overview
The Xilinx Design Constraints (XDC) file template provides for designs targeting the SP605
evaluation board. Net names in the constraints correlate with net names on the latest SP605
evaluation board schematic. Identify the appropriate pins and replace the net names with
net names in the user RTL.
See the Constraints Guide (UG625)
Note:
(nonadjustable). The 2.5V rail cannot be turned off. The SP605 VITA 57.1 FMC interfaces are
compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.
Note:
Evaluation Kit
SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019
The SP605 board VADJ voltage for the FMC LPC connector J2 is fixed at 2.5V
The latest version of the Xilinx constraint file can be found on the
website.
www.xilinx.com
[Ref 12]
for more information.
Appendix C
Spartan-6 FPGA SP605
65
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