Appendix B: Xilinx Design Constraints; Overview - Xilinx Zynq UltraScale+ ZCU208 User Manual

Xilinx Design Constraints

Overview

The Xilinx design constraints (XDC) file template for the ZCU208 board provides for designs
targeting the ZCU208 evaluation board. Net names in the constraints listed correlate with net
names on the latest ZCU208 evaluation board schematic. Identify the appropriate pins and
replace the net names with net names in the user RTL. See the Vivado Design Suite User Guide:
Using Constraints (UG903) for more information.
The HSPC FMCP connector J28 is connected to Zynq
by the variable voltage VADJ_FMC. The FMC bank I/O standards must be uniquely defined by
each customer because different FMC cards implement different circuitry.
IMPORTANT! See the
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
ZCU208 board documentation

Appendix B: Xilinx Design Constraints

® UltraScale+™ RFSoC U1 banks powered
("Board Files" check box) for the XDC file.
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Appendix B
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