Xilinx ML605 Hardware User's Manual page 18
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- User manual (92 pages) ,
- Hardware tutorial (40 pages) ,
- Manual (22 pages)
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Chapter 1:
ML605 Evaluation Board
The ML605 XC6SVX240T FPGA DDR memory interface performance is documented in the
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics (DS152)
The ML605 DDR3 64-bit wide interface has been tested to 800 MT/s.
The DDR3 interface is implemented in FPGA banks 25, 26, 35, and 36. DCI VRP/N resistor
connections are only implemented banks 26 and 36. DCI functionality in banks 25 and 35 is
achieved in the UCF by cascading DCI between adjacent banks as follows:
Table 1-4
Table 1-4: DDR3 SODIMM Connections
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CONFIG DCI_CASCADE = "36 35";
CONFIG DCI_CASCADE = "26 25";
shows the connections and pin numbers for the DDR3 SODIMM.
U1 FPGA Pin
Schematic Net Name
L14
A16
B16
E16
D16
J17
A15
B15
G15
F15
M16
M15
H15
J15
D15
C15
K19
J19
L15
J11
E13
F13
K11
L11
K13
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DDR3_A0
DDR3_A1
DDR3_A2
DDR3_A3
DDR3_A4
DDR3_A5
DDR3_A6
DDR3_A7
DDR3_A8
DDR3_A9
DDR3_A10
DDR3_A11
DDR3_A12
DDR3_A13
DDR3_A14
DDR3_A15
DDR3_BA0
DDR3_BA1
DDR3_BA2
DDR3_D0
DDR3_D1
DDR3_D2
DDR3_D3
DDR3_D4
DDR3_D5
[Ref
4].
J1 SODIMM
Pin Number
Pin Name
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12_BC_N
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019
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