Xilinx ML630 User Manual
Xilinx ML630 User Manual

Xilinx ML630 User Manual

Virtex-6 hxt fpga optical transmission network evaluation board
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Summary of Contents for Xilinx ML630

  • Page 1 With the principle of “Quality Parts,Customers Priority,Honest Operation,and Considerate Service”,our business mainly focus on the distribution of electronic components. Line cards we deal with include Microchip,ALPS,ROHM,Xilinx,Pulse,ON,Everlight and Freescale. Main products comprise IC,Modules,Potentiometer,IC Socket,Relay,Connector.Our parts cover such applications as commercial,industrial, and automotives areas.
  • Page 2 ML630 Virtex-6 HXT FPGA Optical Transmission Network Evaluation Board User Guide UG828 (v1.0) September 28, 2011...
  • Page 3: Revision History

    Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...
  • Page 4: Table Of Contents

    Online Document ............6 Chapter 1: ML630 Board Features and Operation ML630 Board Features .
  • Page 5 FPGA U2 VGA Debug Connector ......... . . 66 Appendix A: Default Jumper Positions Appendix B: VITA 57.1 FMC HPC Connector Pinout Appendix C: ML630 Master UCF Listing for U1 Appendix D: ML630 Master UCF Listing for U2 Appendix E: ML630C Schematic Page List...
  • Page 6: Preface: About This Guide

    Preface About This Guide This document describes the basic setup, features, and operation of the ML630 Virtex®-6 FPGA HXT Optical Transmission Network (OTN) evaluation board. The ML630 board provides the hardware environment for characterizing and evaluating the GTX and GTH transceivers available on the Virtex®-6 XC6VHX565T-2FFG1924C FPGA.
  • Page 7: Conventions

    Blue text in the current document Refer to “Title Formats” in Chapter 1 for details. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files. www.xilinx.com ML630 Board User Guide UG828 (v1.0) September 28, 2011...
  • Page 8: Chapter 1: Ml630 Board Features And Operation

    Chapter 1 ML630 Board Features and Operation This chapter describes the components, features, and operation of the ML630 Virtex®-6 HXT FPGA Optical Transmission Network (OTN) evaluation board. The ML630 board provides the hardware environment for characterizing and evaluating the GTX and GTH transceivers available on the Virtex -6 XC6VHX565T-2FFG1924C FPGA.
  • Page 9: Detailed Description

    This section of the user guide is intended to be read in conjunction with reference to the ML630 (pdf) Schematic 0381388. The ML630 board hosts a complicated clocking system and intricate FPGA-to-FPGA and Interlaken connector connectivity which the schematic helps clarify.
  • Page 10: Virtex-6 Hxt Xc6Vhx565T-2Ffg1924 Fpga U1 And U2

    Detailed Description X-Ref Target - Figure 1-2 UG828_c1_02_080411 Figure 1-2: Detailed Description of ML630 Board Components Virtex-6 HXT XC6VHX565T-2FFG1924 FPGA U1 and U2 FPGA U1 FPGA U2 ML630 12 VDC Power Input Main power on-off “soft” slide switch (SW1) U1/U2 12V DIN4 connectors (J122 and J75)
  • Page 11: Fpga U1 Power Regulators

    Chapter 1: ML630 Board Features and Operation FPGA U1 Power Regulators U1 V (U10/U41) and V (U12) TI PTD08A020W regulators CCINT CCAUX 10. U1 GTX (U4, U5) TI PTD08A101W regulators 11. U1 GTH (U3, U14, U21, U20) TI PTD08A010W and PTD08A006W regulators FPGA U2 Power Regulators 12.
  • Page 12: Fpga U2 Fci Airmax Interlaken Connectors

    (six ports wired to the Si570 oscillators, two ports wired to the 8x8 crosspoint switches); U1 I C: HPC FMC1 J290; U2 I C: HPC FMC2 J104 ML630 HPC FMC Connectors 48. FMC1 connector (J290) 49. FMC2 connector (J104) Default Jumper Positions...
  • Page 13: Monitoring Voltage And Current

    J102. Note: Use of a switchable “power bar” (multiple outlet power strip) is recommended for the two ML630 AC adapters. The two adapters can then be turned on and off simultaneously via the power bar on-off switch. Caution! Only use two power supplies of the same type. Power the ML630 board through two connectors at the same time (J122 and J75 or J141 and J102, depending on power supply type).
  • Page 14 U2 Power System PTD08A006W-U2 MGTXAVTT U2_MGTXAVTT 1.20V 1.20V@6A max CH:4A 67 PTH12000W-Board-wide VCC3V3 VCC3V3 3.30V Fixed 3.30V@6A max U6 8 UG828_c1_03_091311 Figure 1-3: ML630 Board FPGA U1 Power Block Diagram ML630 Board User Guide www.xilinx.com UG828 (v1.0) September 28, 2011...
  • Page 15 1.10V@6A max CH:2A 107 PTD08A006W-U2 MGTHAVTT U2_MGTHAVTT 1.20V 1.20V@6A max CH:3A 108 PTD08A006W-U2 MGTHAVCCPLL U2_MGTHAVCCPLL 1.80V 1.80V@6A max CH:4A 109 UG828_c1_04_081211 Figure 1-4: ML630 Board FPGA U2 Power Block Diagram www.xilinx.com ML630 Board User Guide UG828 (v1.0) September 28, 2011...
  • Page 16 Detailed Description The ML630 board uses power regulators and PMBus compliant digital PWM system controllers from Texas Instruments to supply the U1 and U2 voltages listed in Table 1-1. Table 1-1: ML630 Onboard Power System Devices Reference Typical Device Description...
  • Page 17: Disabling Fpga Onboard Power

    The FPGA Embedded JTAG option is chosen by connecting a USB A-to-Mini-B cable to ML630 USB Mini-B connector J20. The USB A end of the cable plugs into the user's PC, which hosts the Xilinx FPGA configuration software tool (either ChipScope™ Pro or Impact) which is then used to configure the two ML630 FPGAs.
  • Page 18: System Ace Controller Reset

    FPGA. The INIT LED (DS20) lights during FPGA initialization. The DONE LED (DS56) indicates the state of the DONE pin of the FPGA. When the DONE pin is High, the DONE LED lights indicating that the FPGA is successfully configured. ML630 Board User Guide www.xilinx.com UG828 (v1.0) September 28, 2011...
  • Page 19: Fpga U1 User Leds, Dip And Pushbutton Switches

    Chapter 1: ML630 Board Features and Operation FPGA U1 User LEDs, DIP and Pushbutton Switches Figure 1-2 callout [22] DS10 through DS17 are eight active-High LEDs that are connected to user I/O pins on FPGA U1 as shown in Table 1-3.
  • Page 20: User Push Buttons (Active High)

    FPGA U1 USB to UART Bridge Figure 1-2 callout [24] Communications between the ML630 board FPGA U1 and a host computer are accomplished through a USB cable connected to J54. Control is provided by U26, a USB to UART bridge (Silicon Laboratories CP2103).
  • Page 21: References

    Bidirectional differential serial data (P-side) Not used The CP2103 supports an I/O voltage range of 2.5V on the ML630 board. The connections between FPGA U1 and CP2103 should use the LVCMOS25 I/O standard. UART IP (for example, Xilinx® XPS UART Lite) must be implemented in the FPGA logic. FPGA U1 supports the USB to UART bridge using four signal pins: •...
  • Page 22: Fpga U1 200 Mhz 2.5V Lvds Oscillator

    FPGA U1 200 MHz 2.5V LVDS Oscillator Figure 1-2 callout [25] The ML630 board has one SiTime 2.5V LVDS differential fixed 200 MHz oscillator per FPGA. Oscillator U22 (located on the bottom of the board) is connected to FPGA U1 as listed in Table 1-10.
  • Page 23: Fpga U2 User Dip Switches (Active High)

    Chapter 1: ML630 Board Features and Operation FPGA U2 User DIP Switches (Active High) Figure 1-2 callout [27] FPGA U1 DIP switch SW16 provides a set of eight active-High switches that are connected to user I/O pins on the FPGA as shown in Table 1-12.
  • Page 24: Fpga U2 User Gpio Header

    Bidirectional differential serial data (P-side) Not used8 The CP2103 supports an I/O voltage range of 2.5V on the ML630 board. The connections between FPGA U2 and CP2103 should use the LVCMOS25 I/O standard. UART IP (for example, Xilinx® XPS UART Lite) must be implemented in the FPGA logic. FPGA U2 supports the USB to UART bridge using four signal pins: •...
  • Page 25: References

    Chapter 1: ML630 Board Features and Operation Table 1-16: FPGA U2 to U79 (CP2103 Bridge) Connections FPGA U2 Pin FPGA Function Net Name U79 Pin U79 Function RTS, output U2_USB_CTS_I CTS, input CTS, input U2_USB_RTS_O RTS, output TX, data out...
  • Page 26: Fpga U1 Fci Airmax Interlaken Connectors

    Table 1-24 show FPGA U1 to FCI connector details. Refer to the block diagram on the ML630 schematic, page 2, for an overview of the connectivity shown in these tables. ML630 Board User Guide www.xilinx.com UG828 (v1.0) September 28, 2011...

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