Appendix B: Xilinx Constraints File; Overview - Xilinx KCU116 User Manual

Xilinx Constraints File

Overview

®
The Xilinx design constraints (XDC) file template for the KCU116 board is for designs
targeting the KCU116 evaluation board. Net names in the constraints correlate with net
names on the latest KCU116 evaluation board schematic. Users must identify the
appropriate pins and replace the net names with net names in the user RTL. See the Vivado
Design Suite User Guide: Using Constraints (UG903)
The FMC connector J5 (HPC0) is connected to a 1.8V V
cards implement different circuitry, the FMC bank I/O standards must be uniquely defined
by each customer.
The XDC file can be accessed on the
IMPORTANT:
website.
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
[Ref 13]
ADJ
Kintex UltraScale+ FPGA KCU116 Evaluation Kit
www.xilinx.com
Appendix B
for more information.
bank. Because different FMC
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