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Xilinx Design Constraints
The AC701 board Xilinx Design Constraints (XDC) file template provides for designs targeting the
AC701 board. Net names in the constraints correlate with net names on the AC701 board schematic.
You must identify the appropriate pins and replace the net names in this list with net names in the
user RTL. For more information, see Vivado Design Suite User Guide, Using Constraints (UG903)
[Ref
The FMC HPC connector J30 is connected to a 2.5V V
implements customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by
each customer.
Refer to the Board Files area under the Documentation tab on the
Kit product page
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
12].
for the latest constraints file.
www.xilinx.com
Appendix C
bank. Because each user FMC card
CCO
Virtex-7 FPGA AC701 Evaluation
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