Appendix C: Xilinx Design Constraints; Overview - Xilinx ZC702 User Manual

Xilinx Design Constraints

Overview

The ZC702 Xilinx® Design Constraints (XDC) template provides for designs targeting the
ZC702 board. Net names in the constraints correlate with net names on the latest ZC702
board schematic. You must identify the appropriate pins and replace the net names below
with net names in your RTL.
See the Vivado Design Suite User Guide: Using Constraints (UG903)
information.
The FMC LPC connectors J3 and J4 are connected to 2.5V VADJ banks. Because different
FMC cards implement different circuitry, the FMC bank I/O standards must be uniquely
defined by each customer.
The ZC702 ucf/xdc files are under the Documentation tab of the
Note:
Evaluation Kit product
entry, and expand the Associated File(s) list.
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
page. Click the Board Files check box, find the XTP185 ZC702 Schematics
www.xilinx.com
Appendix C
[Ref 12] for more
Zynq-7000 SoC ZC702
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