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Xilinx ML50 Series User Manual

Xilinx ML50 Series User Manual

Evaluation platform
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ML501 Evaluation
Platform
User Guide
UG226 (v1.3) November 10, 2008
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  • Page 1 ML501 Evaluation Platform User Guide UG226 (v1.3) November 10, 2008...
  • Page 2 Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.

  • Page 3: Table Of Contents

    20. Xilinx XC95144XL CPLD ........
  • Page 4 23. Xilinx XCF32P Platform Flash PROM Configuration Storage Device ..30 24. JTAG Configuration Port ..........30 25.

  • Page 5: Preface: About This Guide

    ML501 board • Appendix B, “References” Additional Documentation The following documents are also available for download at http://www.xilinx.com/virtex5. • Virtex-5 FPGA Family Overview The features and product selection of the Virtex-5 FPGA family are outlined in this overview.

  • Page 6: Additional Support Resources

    Additional Support Resources To search the database of silicon and software questions and answers, or to create a technical support case in WebCase, see the Xilinx® website at: http://www.xilinx.com/support. Typographical Conventions This document uses the following typographical conventions. An example illustrates each convention.

  • Page 7: Online Document

    Cross-reference link to a Figure 5 in the Virtex-5 Data Red text location in another document Sheet Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest documentation. ML501 Evaluation Platform www.xilinx.com UG226 (v1.3) November 10, 2008...
  • Page 8 Preface: About This Guide www.xilinx.com ML501 Evaluation Platform UG226 (v1.3) November 10, 2008...

  • Page 9: Chapter 1: Ml501 Evaluation Platform

    Serial Peripheral Interface™ (SPI) Flash (2 MB) • 10/100/1000 tri-speed Ethernet PHY transceiver • USB interface chip with host and peripheral ports • Piezo audio transducer • Rechargeable lithium battery to hold FPGA encryption keys ML501 Evaluation Platform www.xilinx.com UG226 (v1.3) November 10, 2008...

  • Page 10: Package Contents

    For information about the Virtex-5 family of FPGA devices, including product highlights, data sheets, user guides, and application notes, see the Virtex-5 FPGA website at www.xilinx.com/virtex5. Additional information is available from the data sheets and application notes from the component manufacturers.

  • Page 11: Block Diagram

    6A Switching Regulator To PROM To DDR2 SO-DIMM 0.9V TPS51100 3A LDO To V TTVREF 0.9V TPS51100 3A LDO To V UG226_03_083006 Figure 1-1: Virtex-5 FPGA ML501 Evaluation Platform Block Diagram ML501 Evaluation Platform www.xilinx.com UG226 (v1.3) November 10, 2008...

  • Page 12: Detailed Description

    Figure 1-3, page 13 (back). The numbered sections on the pages following the figures contain details on each feature. UG226_01_111507 Figure 1-2: Detailed Description of Virtex-5 FPGA ML501 Evaluation Platform Components (Front) www.xilinx.com ML501 Evaluation Platform UG226 (v1.3) November 10, 2008...
  • Page 13 Note: The label on the CompactFlash (CF) card shipped with your board might differ from the one shown. UG226_02_083006 Figure 1-3: Detailed Description of Virtex-5 FPGA ML501 Evaluation Platform Components (Back) ML501 Evaluation Platform www.xilinx.com UG226 (v1.3) November 10, 2008...

  • Page 14: Virtex-5 Fpga

    Chapter 1: ML501 Evaluation Platform 1. Virtex-5 FPGA A Xilinx Virtex-5 FPGA, XC5VLX50-1FFG676, is installed on the Evaluation Platform (the board). Configuration The board supports configuration in all modes: JTAG, Master Serial, Slave Serial, Master SelectMAP, Slave SelectMAP, Byte-wide Peripheral Interface (BPI) Up, BPI Down, and SPI modes.

  • Page 15: Digitally Controlled Impedance

    Yes, 49.9Ω resistors are installed. Yes, 49.9Ω resistors are installed. Yes, 49.9Ω resistors are installed. Yes, 49.9Ω resistors are installed. Yes, 49.9Ω resistors are installed. Not supported. Yes, 49.9Ω resistors are installed. ML501 Evaluation Platform www.xilinx.com UG226 (v1.3) November 10, 2008...

  • Page 16: Ddr2 Sodimm

    The board is only tested for DDR2 SDRAM operation at a 400 MHz data rate. Faster data rates might be possible but are not tested. MIG Compliance The ML50x DDR2 interface is MIG pinout compliant. The MIG DDR2 routing guidelines outlined in the Xilinx Memory Interface Generator (MIG) User Guide [Ref 13] have been achieved.
  • Page 17 This allows the FPGA to drive a precision clock to an external device such as a piece of test equipment. Table 1-3 summarizes the differential SMA clock pin connections. Table 1-3: Differential SMA Clock Connections Label Clock Name FPGA Pin SMA_DIFF_CLK_IN_N SMA_DIFF_CLK_IN_P SMA_DIFF_CLK_OUT_N SMA_DIFF_CLK_OUT_P ML501 Evaluation Platform www.xilinx.com UG226 (v1.3) November 10, 2008...

  • Page 18: Oscillator Sockets

    33 MHz to the Xilinx System ACE CF (U2) • 33 MHz, 27 MHz, and a differential 200 MHz clock to the Xilinx FPGA If users change the factory default configuration of the clock generator chip, the related reference design material might not work as designed. Instructions for returning the...

  • Page 19: User And Error Leds (Active-High)

    GPIO LED 2 Green DS14 GPIO LED 3 Green DS13 GPIO LED 4 Green DS12 GPIO LED 5 Green DS11 GPIO LED 6 Green DS10 GPIO LED 7 Green Error 1 Error 2 ML501 Evaluation Platform www.xilinx.com UG226 (v1.3) November 10, 2008...

  • Page 20: User Pushbuttons (Active-High)

    FPGA I/O, and they can be used as independent single-ended nets. The of these signals can be set to 2.5V or 3.3V by setting jumper J20. Table 1-9, page 21 CCIO summarizes the differential connections on this expansion I/O connector. www.xilinx.com ML501 Evaluation Platform UG226 (v1.3) November 10, 2008...
  • Page 21 HDR2_2 HDR2_8 HDR2_6 HDR2_12 HDR2_10 HDR2_16 HDR2_14 HDR2_20 HDR2_18 HDR2_24 HDR2_22 HDR2_28 HDR2_26 HDR2_32 HDR2_30 HDR2_36 HDR2_34 HDR2_40 HDR2_38 HDR2_44 HDR2_42 HDR2_48 HDR2_46 HDR2_52 HDR2_50 HDR2_56 HDR2_54 HDR2_60 HDR2_58 HDR2_64 HDR2_62 ML501 Evaluation Platform www.xilinx.com UG226 (v1.3) November 10, 2008...

  • Page 22: Single-Ended Expansion I/O Connectors

    Schematic Net Name FPGA Pin HDR1_2 HDR1_4 HDR1_6 HDR1_8 HDR1_10 HDR1_12 HDR1_14 HDR1_16 HDR1_18 HDR1_20 HDR1_22 HDR1_24 HDR1_26 HDR1_28 HDR1_30 HDR1_32 HDR1_34 AB25 HDR1_36 HDR1_38 HDR1_40 HDR1_42 HDR1_44 HDR1_46 HDR1_48 HDR1_50 HDR1_52 HDR1_54 www.xilinx.com ML501 Evaluation Platform UG226 (v1.3) November 10, 2008...

  • Page 23: Other Expansion I/O Connectors

    The ML501 expansion connector is backward compatible with the expansion connectors on the ML40x, ML32x, and ML42x boards, thereby allowing their daughter cards to be used with the ML501 Evaluation Platform. Table 1-11, page 24 summarizes the additional expansion I/O connections. ML501 Evaluation Platform www.xilinx.com UG226 (v1.3) November 10, 2008...
  • Page 24 GPIOLED 0 GPIO LED 0 GPIOLED 1 GPIO LED 1 GPIOLED 2 GPIO LED 2 GPIOLED 3 GPIO LED 3 Not Connected Not Connected IIC_SCL_EXP Expansion IIC SCL IIC_SDA_EXP Expansion IIC SDA www.xilinx.com ML501 Evaluation Platform UG226 (v1.3) November 10, 2008...

  • Page 25: Stereo Ac97 Audio Codec

    LCD to be removed from the board to access to the components below it. Caution! Care should be taken not to scratch or damage the surface of the LCD window. ML501 Evaluation Platform www.xilinx.com UG226 (v1.3) November 10, 2008...

  • Page 26: Iic Bus With 8-Kb Eeprom

    5V power jack, which also powers the rest of the board. Caution! Care must be taken to ensure that the power load of any attached PS/2 devices does not overload the AC adapter. www.xilinx.com ML501 Evaluation Platform UG226 (v1.3) November 10, 2008...

  • Page 27: System Ace And Compactflash Connector

    CompactFlash, with the xilinx.sys file located in the root directory. The xilinx.sys file is used by the System ACE CF controller to define the project directory structure, which consists of one main folder containing 8 sub-folders used to store the 8 ACE files containing the configuration images.

  • Page 28: Zbt Synchronous Sram

    20. Xilinx XC95144XL CPLD A Xilinx XC95144XL CPLD provides general-purpose glue logic for the board. The CPLD is located under the removable LCD and is not visible in Figure 1-2.

  • Page 29: Usb Controller With Host And Peripheral Ports

    J30 through an RS-232 transceiver to assist with debug. Jumper J50 can be installed to prevent the USB controller from executing firmware stored in the IIC EEPROM. ML501 Evaluation Platform www.xilinx.com UG226 (v1.3) November 10, 2008...

  • Page 30: Xilinx Xcf32P Platform Flash Prom Configuration Storage Device

    The JTAG configuration port for the board (J1) allows for device programming and FPGA debug. The JTAG port supports the Xilinx Parallel Cable III, Parallel Cable IV, or Platform USB cable products. Third-party configuration products might also be available. The JTAG chain can also be extended to an expansion board by setting jumper J21 accordingly.

  • Page 31: Ac Adapter And Input Power Switch/Jack

    The DONE LED indicates the status of the DONE pin on the FPGA. It should be lighted when the FPGA is successfully configured. 30. Program Switch This switch grounds the FPGA's Prog pin when pressed. This action clears the FPGA. ML501 Evaluation Platform www.xilinx.com UG226 (v1.3) November 10, 2008...

  • Page 32: Configuration Address And Mode Dip Switches

    Slave Serial (Platform Flash PROM, up to four configurations) 32. Encryption Key Battery An onboard rechargeable lithium battery is connected to the V pin of the FPGA to BATT hold the encryption key for the FPGA. www.xilinx.com ML501 Evaluation Platform UG226 (v1.3) November 10, 2008...

  • Page 33: Spi Flash

    SMA-based test equipment or cables to be connected to the FMC connectors. Note: Xilinx is not responsible for damage caused by a user attempting to solder the FMC connectors onto the board. ML501 Evaluation Platform www.xilinx.com...

  • Page 34: System Monitor

    (VP/VN) and 16 user selectable analog inputs, known as auxiliary analog inputs (VAUXP[15:0], VAUXN[15:0]). The System Monitor is fully functional on power up, and measurement data can be accessed via the JTAG port pre-configuration. The Xilinx ChipScope™ Pro tool provides access to the System Monitor over the JTAG port.
  • Page 35 HDR2_24_SM_10_P VAUXN[11] J4-26 HDR2_26_SM_11_N VAUXP[11] J4-28 HDR2_28_SM_11_P VAUXN[12] J4-46 HDR2_46_SM_12_N VAUXP[12] J4-48 HDR2_48_SM_12_P VAUXN[13] J4-54 HDR2_54_SM_13_N VAUXP[13] J4-56 HDR2_56_SM_13_P VAUXN[14] J4-42 HDR2_42_SM_14_N VAUXP[14] J4-44 HDR2_44_SM_14_P VAUXN[15] J4-34 HDR2_34_SM_15_N VAUXP[15] J4-36 HDR2_36_SM_15_P ML501 Evaluation Platform www.xilinx.com UG226 (v1.3) November 10, 2008...

  • Page 36: Configuration Options

    The following section provides an overview of the possible ways the FPGA can be configured. JTAG (Xilinx Download Cable and System ACE Controller) Configuration The FPGA, Platform Flash PROM, and CPLD can be configured through the JTAG port. The JTAG chain of the board is illustrated in Figure 1-5.

  • Page 37: Platform Flash Prom Configuration

    Data stored in SPI can be used to program the FPGA. The configuration mode DIP switches must be set to 001 for SPI configuration. When set correctly, the FPGA is programmed upon power-up or whenever the Prog button is pressed. ML501 Evaluation Platform www.xilinx.com UG226 (v1.3) November 10, 2008...
  • Page 38 Chapter 1: ML501 Evaluation Platform www.xilinx.com ML501 Evaluation Platform UG226 (v1.3) November 10, 2008...

  • Page 39: Appendix A: Programming The Idt Clock Chip

    • Xilinx download cable • JTAG flying wires Downloading to the ML50x Board Connect a Xilinx download cable to the board using flying leads connected to jumper (Figure A-1). CLK Prog 3.3V UG226_apdx_a_01_031207 Figure A-1: J3 IDT5V9885 JTAG Connector Click Start →...
  • Page 40 Figure A-2: Programming the IDT5V9885 on the ML50x Using iMPACT To finish programming the chip, cycle the power by turning off the board power switch. After turning the board back on, verify that the clock frequencies are correct. www.xilinx.com ML501 Evaluation Platform UG226 (v1.3) November 10, 2008...
  • Page 41 Memory Solutions Web page offers the following material supporting the Memory Interface Generator (MIG) tool: 12. WP260, Memory Interfaces Made Easy with Xilinx FPGAs and the Memory Interface Generator. 13. UG086, Xilinx Memory Interface Generator (MIG) User Guide (for registered users). Demos on Demand, Memory Interface Solutions with Xilinx FPGAs.

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