Table 5: Chipset Set > Pch-Io Configuration Sub-Screens And Functions; Figure 69: Pch-Io Configuration Menu Initial Screen - Kontron KBox C-102 Series User Manual

1.2.3.2. Chipset > PCH-IO Configuration

Figure 69: PCH-IO Configuration Menu Initial Screen

The following table shows the PCH-IO sub-screens and functions, and describes the content. Default settings are in
bold and some functions include additional information.
Table 10: Chipset Set > PCH-IO Configuration Sub-Screens and Functions
Function Second level Sub-Screen / Description
PCI Express PCI Express
Configuration> Clock Gating>
Legacy IO Low
Latency>
DMI Link ASPM
Control>
PCIE Port
Assigned toLAN>
Port8xh Decode>
Peer Memory
Write Enable>
Compliance Test
Mode>
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PCI Express clock gating for each root port
[Enabled, Disabled]
Enables low latency of legacy I/O as some systems require lower I/O
latency irrespective of power. This is a tradeoff between power and I/O
latency.
[Enabled, Disabled]
Control of Active State Power Management on SA side of DMI link
[Enabled, Disabled]
Read Only file
This port is always 5.
[5]
PCI express port 8xh decode
[Enabled, Disabled]
Enables/disables peer memory write
[Enabled, Disabled]
Enable when using compliance load board
[Enabled, Disabled]
KBox C-102 - User Guide, Rev. 1.0
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