Kontron cPCI-MXS64GX Technical Reference Manual
Kontron cPCI-MXS64GX Technical Reference Manual

Kontron cPCI-MXS64GX Technical Reference Manual

6u compactpci 64-bit system processor
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cPCI-MXS64GX
6U CompactPCI 64-BIT System Processor
Technical Reference Manual
Version 1.4, May 2002
Note: The latest releases of the Technical Reference Manuals are available at:
ftp://ftp.kontron.ca/Support/Product_Manuals/
www.kontron.com
Ref. : M6004_TECH

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Summary of Contents for Kontron cPCI-MXS64GX

  • Page 1 6U CompactPCI 64-BIT System Processor Technical Reference Manual Version 1.4, May 2002 Note: The latest releases of the Technical Reference Manuals are available at: ftp://ftp.kontron.ca/Support/Product_Manuals/ www.kontron.com Ref. : M6004_TECH...
  • Page 2 Section 2 : Removed UPDATING OR RESTORING THE BIOS IN FLASH Replaced by : VT100 MODE Added the note : UPDATING OR RESTORING THE BIOS IN FLASH (see the Kontron WEB site and select the “support” section) Page E.5 J4 Row A, pin 5 - DS4- changed for SD4-...
  • Page 3 Historical (continued) May 13, 2002 Replace all occurrences of Teknor Applicom Inc or Teknor by Kontron, Inc. - Replace all occurrences of Adaptec and Symbios with LSI. - Replace in section 3.3.3.1 "...from "8MB to 1.5GB of..." by "... from 32MB to 1.5GB of...
  • Page 4 FCC COMPLIANCE STATEMENT Warning Changes or modifications to this unit not expressly approved by the party responsible for the compliance could void the user’s authority to operate this equipment. This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC rules.
  • Page 5 This document may contain information or refer to products protected by the copyrights or patents of others and does not convey any license under the patent rights of Kontron, nor the rights of others. Printed in Canada.
  • Page 6 READ ME FIRST Your computer board has a standard non-rechargeable lithium battery. To preserve the battery lifetime, the battery enable jumper is removed when you receive the board. If you do not have any jumper cap, we suggest you to use the Watchdog Timer jumper cap. EXERCISE CAUTION WHILE REPLACING LITHIUM BATTERY WARNING Danger of explosion if battery is incorrectly replaced.
  • Page 7 ADAPTER CABLES While adapter cables are provided from various sources, the pinout is often different. The direct crimp design offered by Kontron allows the simplest cable assembly. All cables are available from Kontron Sales Department.
  • Page 8 After opening the box, save it and the packing material for possible future shipment. Remove the board from its antistatic wrapping and place it on a grounded surface. Inspect the board for damage. If there is any damage, or items are missing, notify Kontron immediately. When unpacking you will find: ®...
  • Page 9: Table Of Contents

    1.2. Product Specifications......................1.2 1.3. Hot Swap capability ......................1.4 1.4. Interfacing with the Environment ..................1.6 1.4.1. CPCI ........................1.6 1.4.2. Mezzanine ......................1.6 1.5. Compatibility with other KONTRON Products..............1.7 1.6. Mezzanine Card Concept....................1.8 1.6.1. Kontron’s Mezzanine Concept................1.9 1.6.2. PMC Concept......................1.9 1.6.3. CompactFlash Feature ..................1.9 ONBOARD FEATURES 2.1.
  • Page 10 2.4. Floppy Disk Interface .......................2.4 2.5. PS/2 Keyboard / PS/2 Mouse Interface ................2.5 2.6. Parallel Port ........................2.5 2.6.1. Standard Mode....................2.6 2.6.2. EPP Mode ......................2.6 2.6.3. ECP Mode......................2.7 2.7. Power Management ......................2.7 2.8. SCSI Interface .........................2.7 2.9. Serial Ports ........................2.8 2.9.1. SERIAL PORT 1....................2.9 2.9.1.1.
  • Page 11 INSTALLING THE BOARD 3.1. Setting Jumpers .......................3.1 3.1.1. Jumper Description for the CPCI-MXS64GX ............3.1 3.1.2. CPCI-MXS64GX – Jumper Settings ..............3.2 3.1.3. Register’s description RS232/RS485..............3.3 3.1.4. History and monitor status ...................3.3 3.1.5. Multimedia, History status ...................3.4 3.1.6. Monitoring status and I/O access.................3.4 3.1.7.
  • Page 12 3.3. Customizing the Board....................3.15 3.3.1. Processor and Fan ....................3.15 3.3.2. Backup Battery....................3.16 3.3.3. Memory ......................3.17 3.3.3.1. SDRAM System Memory..............3.17 3.3.3.2. DIMM Installation.................3.18 3.3.4. Supervision Features ..................3.19 3.3.4.1. Power Fail Monitoring................3.19 3.3.4.2. Watchdog ....................3.20 3.3.4.3. Thermal Management .................3.22 3.4. Building a CPCI System....................3.23 3.4.1.
  • Page 13 3.5. CPCI I/O Signals......................3.30 3.5.1. J3 Signal Specification ..................3.30 3.5.1.1. Ethernet LEDS ..................3.30 3.5.1.2. Ethernet 1....................3.30 3.5.1.3. Serial Port 3 ..................3.30 3.5.1.4. Serial Port 4 ..................3.31 3.5.1.5. IDE LED Signals..................3.31 3.5.1.6. IR Serial Port 2 ..................3.31 3.5.1.7. Hot Swap HA (High Availability) signals..........3.31 3.5.1.8.
  • Page 14 SOFTWARE SETUPS 4.1. BIOS Setup Program .......................4.1 4.1.1 Accessing the BIOS setup program..............4.1 4.1.2 Main Menu ......................4.3 4.1.3 Setups.........................4.4 4.1.4 Standard CMOS Setups ..................4.5 4.1.5 Saving & Exiting Operations ................4.5 4.1.6 BIOS Features Setup ..................4.6 4.1.7 Chipset Features Setup..................4.8 4.1.8 Power Management Setup ................4.10 4.1.9 PnP/PCI Configuration ..................4.12...
  • Page 15 D.1 Top Devices Surface Mount.................... D-1 D.2 Assembly Bottom Diagram ..................... D-2 D.3 Mounting Holes ....................... D-3 D.4 Connector Holes ......................D-4 CONNECTOR PINOUTS....................E-1 cPCI-MXS64GX Connectors and Headers ..............E-1 J1 CPCI Bus ........................E-2 J2 CPCI Bus ........................E-3 J3 CPCI Bus ........................E-4...
  • Page 16 J4 CPCI Bus ........................E-5 J5 CPCI Bus ........................E-6 J12, Video (VGA)......................E-6 J13, Serial Port 1 - RS-232 ..................... E-7 J14, mezzanine PCI......................E-7 E.10 J15/J16, Ethernet 1 and 2 ....................E-8 E.11 J17, PS/2 Keyboard/Mouse .................... E-8 E.12 J18, CompactFlash Disk....................
  • Page 17: Product Description

    1. PRODUCT DESCRIPTION PRODUCT OVERVIEW SPECIFICATIONS HOT SWAP CAPABILITY INTERFACING WITH THE ENVIRONMENT COMPATIBILITY WITH KONTRON PRODUCTS MEZZANINE CONCEPTS...
  • Page 18: Product Overview

    Rear I/O CPCI connectors are PICMG 2.0 Rev 3.0 compliant. CompactPCI connectors are located at the rear edge of the processor board. The complete CPCI connector configuration of the cPCI-MXS64GX is composed of four connectors referred to as J1, J2, J3, J4, and J5. Their function is described below: 32 bit PCI signaling, power 64 bit extension, arbitration, clocks, reset and.
  • Page 19: Product Specifications

    Technical Reference manual 1.2. PRODUCT SPECIFICATIONS The cPCI-MXS64GX industrial system processor features: • ® Intel’s enhanced performance Pentium processor. Low power Mobile Pentium®III 500 and 700MHz, 256KB on-die L2 pipelined burst cache. • 440GX AGP set. • Supporting up to 1.5GB SDRAM with parity or ECC.
  • Page 20 • Two year warranty. The cPCI-MXS64GX can be purchased either for front plate I/O interfacing (video serial port, Ethernet) or RTM (Rear Transition Module) I/O interfacing (no interconnection capability available on the front plate) through CPCI I/O connectors and backplane.
  • Page 21: Hot Swap Capability

    Hot Swap consists of board hardware with the Hot Swap additions to the Hardware Connection Layer, and the Hot-Plug Service. Upon insertion of the board (any hot swappable board but the system host, cPCI-MXS64GX, the hardware connection layer will initialize the board and the Hot-Plug Service provides the means for reconfiguring the system.
  • Page 22 Product Description The Software Connection Control resources on the board provide a signal (ENUM#) for system host notification and a switch and LED to interface with the operator. Full Hot Swap boards drive the ENUM# signal to the system host to indicate a service request.
  • Page 23: Interfacing With The Environment

    CPCI Passive Backplane. 1.4.2. Mezzanine The mezzanine is a hardware interface concept introduced by Kontron to increase the I/O connectivity of the cPCI-MXS64GX, but respecting the dual slot 6U form factor restrictions. The onboard mezzanine connector features PCI bus, IDE, floppy, keyboard and mouse signals, for potential mezzanine applications: Kontron provides an optional storage mezzanine composed with a hard drive, a floppy disk drive.
  • Page 24: Compatibility With Other Kontron Products

    The boards are fully compliant with the PICMG 2.0 Rev.2.1 and PICMG 2.1 CompactPCI specifications. When building a basic environment around the cPCI-MXS64GX, the platform may be composed of any of the following devices: • cPCI-MXS64GX 6U System Processor •...
  • Page 25: Mezzanine Card Concept

    Technical Reference manual 1.6. MEZZANINE CARD CONCEPT The capability of the cPCI-MXS64GX to connect with other devices is enforced by PCI Mezzanine Cards (PMC). A fully equipped cPCI-MXS64GX board may appear as follows:...
  • Page 26: Kontron's Mezzanine Concept

    Product Description 1.6.1. Kontron’s Mezzanine Concept This is Kontron’s concept to expand the I/O capability of the board. It is built around two connectors: • Mezzanine connector handling IDE and floppy disk drive signals. • Mezzanine connector handling a complete PCI signal set (primary bus) including the REQ/GNT arbitration signal pair.
  • Page 27: Onboard Features

    2. ONBOARD FEATURES COMPACTFLASH INTERFACE ENHANCED IDE INTERFACES ETHERNET INTERFACES FLOPPY DISK INTERFACE PS/2 KEYBOARD AND MOUSE INTERFACE PARALLEL PORT POWER MANAGEMENT SCSI INTERFACE SERIAL PORTS THERMAL MANAGEMENT USB INTERFACES VIDEO INTERFACES...
  • Page 28: Compactflash Interface

    (typical M.T.B.F. is 1,000,000 hours) and low power. The cPCI-MXS64GX supports all CompactFlash sizes presently available and future sizes when available. The C-Flash disk connects on the cPCI-MXS64GX via the onboard Flash Disk connector. Related Jumpers cPCI-MXS64GX: W3 to set the CompactFlash disk as master or slave.
  • Page 29: Enhanced Ide Interfaces

    Technical Reference Manual 2.2. ENHANCED IDE INTERFACES The board features two channel Bus Master PCI EIDE dedicated to Primary and Secondary IDE logical interfaces. Each channel supports up to two IDE devices (including CD-ROMs, hard disks, plus CompactFlash on the secondary IDE interface) with independent timings, in Master/Slave combination.
  • Page 30: Ethernet Interfaces

    Onboard Features 2.3. ETHERNET INTERFACES Both Ethernet controllers reside on the Primary PCI bus. Each interface supports 10Base-T and 100Base-TX specifications: 10Mbps and 100Mbps network speeds are automatically detected and switched. Signal Path See note on page 1.5. Related Jumpers None.
  • Page 31: Cpci I/O Configuration

    The Boot from LAN capability is supported. To enable the option, use the BIOS Setup program. Please refer to Section 4.1 BIOS Setup Program. A diskette entitled “Network Drivers for Intel 82559 is included with the cPCI-MXS64GX. It contains network drivers for most common operating systems.
  • Page 32: Ps/2 Keyboard / Ps/2 Mouse Interface

    11.3.7 Integrated Peripherals : USB Keyboard Support; PS/2 Mouse Function Control 2.6. PARALLEL PORT The cPCI-MXS64GX features one multi-mode parallel port. It is compatible with Standard Mode IBM PC/XT, PC/AT, and PS/2 compatible bi-directional parallel port, Enhanced Parallel Port (EPP), and Enhanced Capabilities Port (ECP).
  • Page 33: Standard Mode

    Technical Reference Manual The differences between Standard, EPP, and ECP modes appear in the signal assignation of the pins on the connector. Differences are described as follows: Pin Number (J5) Standard Mode EPP Mode ECP Mode SLCT SLCT PERROR...
  • Page 34: Ecp Mode

    Onboard Features EPP mode assumes that the parallel port can be used to connect more than one peripheral device using multiplexor or daisy chain configurations. A multiplexor is an external device that permits up to eight parallel port devices to share a single parallel port.
  • Page 35: Serial Ports

    Technical Reference Manual Signal Path SCSI interface signals are only available through the J3-J4 CPCI I/O connector or through RTM (Rear Transition Module). Related Jumpers W6 – To determine the SCSI termination (hardware, software or disabled) BIOS Settings 11.3.7 Integrated Peripherals: Enable/Disable the Onboard PCI SCSI Chip.
  • Page 36: Serial Port

    Select Com Port Address of Serial Port 1 2.9.1.1. Remote Reset A remote hardware reset of the cPCI-MXS64GX is possible by sending a break on the Serial Port 1 or Serial Port 2 (see section 3.1 for Remote Reset jumper setting). A break is simple an abnormally long start bit (100ms or more) on the incoming data line.
  • Page 37: Front Plate Configuration

    Technical Reference Manual The remote reset will work in RS-232 and RS-422 modes. It will also work with a modem, since the modem will repeat the break signal over the telephone network. All major telecommunication software have the capability of sending a break signal, usually by pressing the CTRL-B keys or the ALT-B keys on the keyboard.
  • Page 38: Infrared Mode

    Onboard Features RS-422 and RS-485 modes allow communication using differential signals through one pair of wires (RS-485) or two (RS-422) to increase the noise immunity during data transfers. RS-422 and RS-485 protocols offer advantages such as increased speed over longer distances or improved reliability over similar RS-232 setups.
  • Page 39: Protocol

    Technical Reference Manual 2.9.3.2. RS-232 Protocol: When configured for RS-232 operation mode, the Serial Port 3 is 100% compatible with the IBM-AT serial port signals. 2.9.3.3. RS-422 Protocol: The RS-422 protocol (Full Duplex) uses both RX and TX lines during a communication session.
  • Page 40: Serial Port

    Onboard Features CAUTION When installing the cPCI-MXS64GX at one end of the network, W8 and W9 jumper caps must be installed to connect the 120 ohms termination resistors (See Section 3.1 – Setting Jumpers). 2.9.4. Serial Port 4 The Serial Port 4 is buffered directly for RS-232 operations and is 16C550 PC-Compatible.
  • Page 41: Usb Interfaces

    Technical Reference Manual The temperature management consists in reducing the CPU clock speed throttling when the temperature goes over the high limit (overheating condition) and suspending the throttling operation as soon as the temperature returns under the low temperature limit (normal condition).
  • Page 42: Video Interface

    USB supports Plug and Play and hot swapping operations (OS level). These user-friendly features allow USB devices to be automatically attached, configured and detached, without reboot or running setup. The cPCI-MXS64GX board fully supports the standard universal host controller interface (UHCI) and uses standard software drivers that are UHCI-compatible. 2.12. VIDEO INTERFACE The high-performance video capability of the board is based on Accelerated Graphics Port (AGP) technology.
  • Page 43: Supported Resolutions

    Technical Reference Manual 2.12.1. Supported Resolutions The maximum video resolution and performance depend directly on the drivers running with your software application. Resolution and number of colors specification are listed below: Resolution Number of Colors 640x480, 800x600, 1024x768, 1280x1024...
  • Page 44: Installing The Board

    3. INSTALLING THE BOARD SETTING JUMPERS REGISTER’S DESCRIPTION ONBOARD INTERCONNECTIVITY CUSTOMIZING THE BOARD BUILDING A CPCI SYSTEM CPCI I/O SIGNALS...
  • Page 45: Setting Jumpers

    3.1. SETTING JUMPERS 3.1.1. Jumper Description for the PCI-MXS64GX Description VT-100 Mode (1-2) When enabled, allows VT100 or ANSI terminal connection Download Mode (3-4) When enabled, allows data serial download from a remote computer. Board Configuration Defines if used with Front Access or Rear Access CompactFlash Setting Use this connector to setup the CompactFlash...
  • Page 46: Cpci-Mxs64Gx - Jumper Settings

    Technical Reference Manual 3.1.2. PCI-MXS64GX – Jumper Settings W4 Battery Connected Disconnected W3 Compact Flash Disk Master Slave Board Configuration Rear Access Front Access W1 VT-100 / Download Mode 8HP Configuration Enable VT-100 mode Reserved 4HP Configuration * Default Setting...
  • Page 47: Register's Description Rs232/Rs485

    Installing the Board 3.1.3. Register’s description RS232/RS485 CPLD Address READ n90h* RS485 RS232 WRITE n90h* RS485 RS232 Power-up Default : Enable RTS2 to be used as 485TX ENABLE when in 485 mode RS232 : Enable UART2 RS232 operation RS485 : Enable UART2 RS422 and 485 operation The serial port 2 mode can be controlled by setting three bits.
  • Page 48: Multimedia, History Status

    Technical Reference Manual 3.1.5. Multimedia, History status CPLD Address READ n92h* WD_LOCK CLRHIS WRITE n92h* WD_LOCK CLRHIS Power-up Default CLRHIS : When low, clear all history bits. Put this bit to 1 to enable history logging. WD_LOCK : When high, lock the state of the enable bit for the digital watchdog 3.1.6.
  • Page 49: Uart 4 Pnp Configuration

    Installing the Board The serial port 3 & 4 interrupt can be controlled in the following way. Bit 1 Bit 0 IRQ 3 IRQ 4 IRQ 5 IRQ 7 The serial port 3 & 4 base address can be controlled in the following way. CBAS Bit 1 Bit 0...
  • Page 50: Nmi Control

    Technical Reference Manual The digital watchdog duration can be controlled in the following way. WDD[2..0] NMI(T) RESET(T) NMI(T)+8T NMI(T)+8T 256T NMI(T)+8T 1024T NMI(T)+8T 4096T NMI(T)+8T 16384T NMI(T)+8T 65536T NMI(T)+8T 262144T NMI(T)+8T Time-out selection with T = 1.08ms (TBC) 3.1.10. NMI control...
  • Page 51: 0Register Bits Description (Summary)

    Installing the Board 3.1.11. 0Register BITs description (summary) Address CPLD READ n90* RS485 RS232 WRITE READ PBRST n91* WRITE READ n92* _CLRHIS WD_LOCK WRITE READ n93* IDCHIP I2C_DATA I2C_CLK WRITE READ n94* _CND3 CIS3_1 CIS3_0 CBAS3_1 CBAS3_0 RESERVED WRITE READ RESERV.
  • Page 52: Onboard Interconnectivity

    Technical Reference Manual 3.2. ONBOARD INTERCONNECTIVITY 3.2.1. cPCI-MXS64GX Block Diagram XTAL Intel CuMine PIII ITP Test Early Power Connector 256KB Switching MPIII Core Clocks MPIII Core L2 Cache Hot Swap Regulators System Clock Synthes. & 500Mhz 500MHz Thermal Controller...
  • Page 53: Mobile Pentium ® Ii / Iii Processor

    Installing the Board The cPCI-MXS64GX is not only a matter of computation power. The boards also provide a high capability to interface with peripherals through three integrated chips: " Host-to-PCI bridge for. 443GX from Intel: interface with the processor (host), system memory, video controller, and Primary PCI bus (3.3V / 33MHz).
  • Page 54: 82371Ab Pci-To-Isa Bridge / Ide Xcelerator (Piix4)

    Technical Reference Manual The PCI-to-PCI bridge allows the Primary and Secondary PCI buses to operate concurrently. This means that a master and a target on the same PCI bus can communicate while the other PCI bus is busy. This traffic isolation may increase system performance in applications where system resources are highly used.
  • Page 55: Onboard Connectors And Headers

    J16/J15 indicators. Mouse and keyboard signals are combined on a Keyboard/Mouse standard 6-pin DSUB female connector. This connector is dedicated to the Kontron’s CompactFlash CompactFlash module to support CompactFlash disk. This connector is implemented to support floppy drive Storage Mezzanine and hard disk signals.
  • Page 56: Front Plate Connectors And Indicators

    Technical Reference Manual 3.2.7. Front Plate Connectors and Indicators Name Description Comments Video Connector Standard 15-pin DSUB female connector Reset Button Use a small tool to press the button and proceed to a hardware reset of the board IDE/SCSI LEDs...
  • Page 57: Faceplate Options

    Installing the Board 3.2.8. FACEPLATE OPTIONS Front Access Rear Access Front Access Front Access Rear Access Rear Access with Floppy with Floppy 3.13...
  • Page 58: Compactpci Connectors

    CPCI J3 Connector Supports serial ports 3, 4 & Infrared, V-Port, Ethernet1, and power signals. " CPCI J2 Connector (P2 on the cPCI-MXS64GX) Supports additional system slot signals, PCI 64-Bit extension, and power. " CPCI J1 Connector (P1 on the cPCI-MXS64GX) Supports CPCI bus signals, and power.
  • Page 59: Customizing The Board

    3.3. CUSTOMIZING THE BOARD 3.3.1. Processor and Fan cPCI-MXS64GX Your board will be installed with the Mobile Pentium III processor, Low Power 500 or 700MHz and its adequate cooling system. Since CPUs are very sensitive components, particular attention should be given while installing a processor on the board.
  • Page 60: Backup Battery

    Technical Reference Manual 3.3.2. Backup Battery An onboard 3.6V lithium battery is provided to backup BIOS setup values and the real time lock (RTC). When replacing, the battery must be connected as follows: 3.6V Lithium Battery Positive Pin (Center)
  • Page 61: Memory

    Installing the Board 3.3.3. Memory 3.3.3.1. SDRAM System Memory The cPCI-MXS64GX supports three 168-pin DIMM (Dual In-Line Memory Module) sockets for memory configuration from 32MB to 1.5GB of Synchronous DRAM. The memory characteristics must conform to the following: " 1.15 inch height, 168-pin DIMM.
  • Page 62: Dimm Installation

    Technical Reference Manual The recommended DIMM devices are listed in the table below. Vendor’s part number DIMM’s description Vendor’s Name CTK32M/P100S ECC SDRAM 32MB 4M*72 PC100 1.15"HT CENTON 4X72CQ2X8S4E ECC SDRAM 32MB 4M*72 PC100 1.15"HT ROCKY MOUNTAIN RAM DIM-200472V2S08G1 ECC SDRAM 32MB 4M*72 PC100 1.15"HT...
  • Page 63: Supervision Features

    Installing the Board 3.3.4. Supervision Features The cPCI-MXS64GX provides a set of programmable I/O registers to setup the Intel PIIX4 (I/O addresses 4030h to 4037h) and the XILINX FPGA (I/O addresses programmable at 190h-193h, 290h-293h or 390h-393h using the AWARD Chipset Features Setup).
  • Page 64: Watchdog

    This feature is useful in embedded systems where human supervision is not required or impossible. The cPCI-MXS64GX provides a two-stage digital watchdog with software programmable time-out period. Following a reset of any source, the watchdog is disabled. The watchdog can be enabled by software.
  • Page 65 Installing the Board A variable refresh is possible as shown below: Write to Register n96h with WDS[2,0] having the value below WatchD og internal counter value 16ms 8.6ms 8.6 ms RESET The programmable watchdog can be viewed as a decrementing counter that is initialized by a write to register n92h.
  • Page 66: Thermal Management

    Technical Reference Manual TIME-OUT The programmable watchdog has two stages: the first stage has a variable time-out while the second stage has a fixed one. The first stage time-out is chosen at runtime from eight preset values (see table below). The first stage time-out generates an NMI interrupt (if enabled in register n92h).
  • Page 67: Building A Cpci System

    Installing the Board 3.4. BUILDING A CPCI SYSTEM When building a CompactPCI system, a minimum requirement consists in: a chassis, a CompactPCI backplane, a storage module, a power supply unit, and a ventilation system. The main AC power is drawn to the chassis components through an IEC power plug with a 2-stage filter, fuse holder and power switch.
  • Page 68: Backplane

    Technical Reference Manual 3.4.1. Backplane An entry-level backplane is provided by Kontron. It is referred to as cBP-08R. It features 8 CPCI slots (one PCI I/O segment), and includes J3-J5 I/O connectors on all slots. A 16-CPCI-slot backplane (cBP-16R) is also available from Kontron. It supports two PCI...
  • Page 69: Rear-Panel I

    Installing the Board 3.4.2. Rear-Panel I/O This feature is intended to issue the I/O capabilities of the system processor to the rear of the enclosure using a Rear I/O Transition module (cTM80-STD2S). The Rear I/O Transition module gathers all the I/O signals of the CPU board and makes them easily accessible through standard headers and connectors located at the rear of enclosure.
  • Page 70 Technical Reference Manual Rev. 3.26...
  • Page 71: Storage Devices

    The ventilation unit of the enclosure conforms to the global requirement of the system in fully loaded configuration. 3.4.6. Installing the Board into a Bay The cPCI-MXS64GX is mechanical Eurocard form factor boards. It takes advantages of the IEEE1101.10 specifications that ensure a mechanical interchange capability between different plug-in elements in sub-racks.
  • Page 72: Connector Keying

    Color coded keys prevent inadvertent installation of a 5V peripheral board in a 3.3V slot. The cPCI-MXS64GX is universal. It does not support coding key. The PCI bus does not require to be keyed. Backplane connectors must always be keyed according to the signaling (VIO) level.
  • Page 73: Bus Mastering

    To install the cPCI-MXS64GX board into a bay, proceed as follows: Locate the 6U system slot Remove the front plate of the slot where you intend to insert the cPCI-MXS64GX. Ensure the module is properly aligned with the guide-rails and slide it gently until...
  • Page 74: Cpci I/O Signals

    Technical Reference Manual 3.5. CPCI I/O SIGNALS This section describes integrated feature signals available on rear panel CPCI I/O connectors (J3, J4, and J5) 3.5.1. J3 Signal Specification 3.5.1.1. Ethernet LEDS Signal Pin Assignation Description SPEEDLED 0-1 A6, E6...
  • Page 75: Ide Led Signals

    Installing the Board 3.5.1.4. Serial Port 4 Signal Pin Assignation Description /DCD4 Data Carrier Detect RXD47 Receive Data /DSR4 Data Set Ready TXD4 Transmit Data /RTS4 Ready To Send /CTS4 Clear To Send /RI4 Ring Indicator /DTR4 Data Terminal Ready 3.5.1.5.
  • Page 76: J4 Signal Specification

    Technical Reference Manual 3.5.2. J4 Signal Specification 3.5.2.1. Power Management Signal Pin Assignation Description I2C-CLK I2C clock signal I2C-DATA I2C data signal Reserved /EXT-FAN0-FAIL Enclosure fan 0 fail /EXT-FAN1-FAIL Enclosure fan 1 fail /SM-BYPASS Reserved 3.5.2.2. SCSI Interface Signal...
  • Page 77: Video Interface

    Installing the Board 3.5.2.3. Video Interface Signal Pin Assignation Description VSDA Video serial data line (video I2C) VSCL Video serial clock line (video I2C) HSYNC Horizontal sync line VSYNC Vertical sync line Analog Red video signal GREEN Analog Green video signal BLUE Analog Blue video signal 3.5.2.4.
  • Page 78: Ide 1 Interface

    Technical Reference Manual 3.5.2.6. IDE 1 Interface Signal Pin Assignation Description /BRSTDRV IDE1_ 0-15 B20, E19, C19, A19, Sec. Disk Data – These signals are used to transfer D18, B18, E17, C17, data to or from the IDE device.
  • Page 79: J5 Signal Specification

    Installing the Board 3.5.3. J5 Signal Specification 3.5.3.1. IDE 0 Interface Signal Pin Assignation Description /BRSTDRV /BRSTDRV PDD 0-15 B4, E3, C3, A3, D2, B2, Prim. Disk Data – These signals are used to transfer E1, C1, D1, A2, C2, E2, data to or from the IDE device.
  • Page 80: Floppy Disk Interface

    Technical Reference Manual 3.5.3.3. Floppy Disk Interface Signal Pin Assignation Description /FD-DRVEN 0-1 E7, A8 Drive 0-1 density select /FD-INDEX Index /FD-MTR 0-1 C8, A9 Motor 0-1 enable /FD-DS 0-1 E8, D8 Drive 0-1 select /FD-DIR Direction /FD-STEP Step pulse...
  • Page 81: Parallel Port

    Installing the Board 3.5.3.6. Parallel Port Signal Pin Assignation Description SLCT Printer select Paper end BUSY Busy signal /ACK Acknowledge handshake PD 0-7 E17, C17, A17, D16, Parallel port data bus C16, B16, A16, E15 /SLCTIN Printer select Auto line feed /INIT Initiate output /ERR...
  • Page 82: Software Setups

    4. SOFTWARE SETUPS BIOS SETUP PROGRAM VT100 MODE...
  • Page 83: Bios Setup Program

    The system BIOS (Basic Input Output System) provides an interface between the operating system and the hardware of the cPCI-MXS64GX system processor. The CPCI-MXS64GX and uses the AWARD Setup program, a setup utility in flash memory that is accessed by pressing the DELETE key at the appropriate time during system boot.
  • Page 84 Technical Reference Manual The main menu of the AWARD BIOS CMOS Setup Utility appears on the screen. KONTRON COMMUNICATIONS INC. T1023 BIOS VERSION 2.0 CMOS SETUP UTILITY AWARD SOFTWARE, INC. (2A69TU00) STANDARD CMOS SETUP LOAD BIOS DEFAULTS BIOS FEATURES SETUP...
  • Page 85: Main Menu

    Software Setups 4.1.2 Main Menu The Main Menu includes the following categories: Category Description Standard CMOS Setup This Setup page includes all the items in a standard, AT-compatible BIOS (date, time, hard disk type, floppy disk type, video adapter type, memory…). BIOS Features Setup This Setup page includes all the items of AWARD’s special enhanced features.
  • Page 86: Setups

    Technical Reference Manual 4.1.3 Setups The arrow keys (↑ ↓ → ←) are used to highlight items on the menu and the PAGEUP and PAGEDOWN keys are used to change the entry values for the highlighted item. To enter in a submenu, press the ENTER key.
  • Page 87: Standard Cmos Setups

    Hard Disks Two IDE controllers are defined on the cPCI-MXS64GX board. The Primary and Secondary controllers can both have two disks: Master Disk or Slave Disk. Only three settings are available for the hard disk type: Auto, User and None. Type 1 to 46 are not predefined in the system: Use auto-detect or enter the parameters for the type in the user-defined.
  • Page 88: Bios Features Setup

    Technical Reference Manual 4.1.6 BIOS Features Setup BIOS Possible Option Setup Defaults Description Defaults Settings Virus Warning Dis. Dis. En. / Dis. When Enabled, you receive a warning message if a program (specifically, a virus) attempts to write to the boot sector or the partition table of the hard disk drive.
  • Page 89 Software Setups BIOS Features Setup (Continued) BIOS Setup Possible Option Description Defaults Defaults Settings Report No FDD For Yes, No Select Yes to release IRQ6 when the system contains no floppy Win 95 drive, for compatibility with Windows 95 logo certification. In the Integrated Peripherals screen, select NO on the Onboard FDC Controller option.
  • Page 90: Chipset Features Setup

    CPU L2 Cache ECC Dis. En./Dis. Enables or Disables ECC Checking for L2 cache. Note: processors provided by Kontron support ECC. Checking However, not all Pentium® II / III processors support ECC. Check Intel’s website to know if your processor supports ECC: http://developer.intel.com/support/...
  • Page 91 Software Setups Chipset Features Setup (Continued) BIOS Setup Possible Option Description Defaults Defaults Settings PCI/VGA Palette Dis. Dis. En./Dis. Palette snooping allows multiple VGA devices operating on Snoop different buses to handle data from the CPU on each set of palette registers.
  • Page 92: Power Management Setup

    Technical Reference Manual 4.1.8 Power Management Setup This part of the setup configures power conservation options. BIOS Setup Possible Option Description Defaults Settings Defaults ACPI Function Dis. En./Dis. The Advanced Configuration and Power Interface (ACPI) allows Operating System Direct Power Management (OSPM) and make advanced configuration architectures possible.
  • Page 93 Software Setups Power Management Setup (Continued) BIOS Setup Possible Option Description Defaults Defaults Settings Resume by Ring Dis. En./Dis. When Enabled and a modem is connected to a serial port, allows a modem ring to re-activate the CPU when in Suspend mode. IRQ 8 Break Suspend Dis.
  • Page 94: Pnp/Pci Configuration

    Technical Reference Manual 4.1.9 PnP/PCI Configuration This part of the setup configures PnP/PCI options. BIOS Setup Possible Option Description Defaults Defaults Settings PNP OS Installed Yes, No If the operating system (OS) is Plug and Play (for example Windows 95), select “Yes” if you want the OS to allocate resources according to Plug and Play standards, or “No”...
  • Page 95: Cpu/Board Features Setup

    Software Setups 4.1.10 CPU/Board Features Setup BIOS Setup Possible Option Description Defaults Defaults Settings Current Processor(s) This option displays the current processor speed. Speed Front Side Bus Speed This option displays the current Front Side Bus speed. This speed is selected by the CPU auto-detection logic. Thermal Management Options: .
  • Page 96: Integrated Peripherals

    Technical Reference Manual 4.1.11 Integrated Peripherals Option BIOS Setup Possible Description Defaults Defaults Settings Select Enabled to activate the Primary/Secondary IDE channel. On-Chip En./Dis. The four options below appear only if the On-Chip Primary option Primary/Secondary is enabled. On-Chip Primary IDE...
  • Page 97: Vt100 Mode

    Technical Reference Manual 4.2. VT100 MODE The VT100 operating mode allows remote setups of the board. This configuration requires a remote terminal that must be connected to the board through a serial communication link. 4.2.1 Requirements The terminal should emulate a VT100 or ANSI terminal. Terminal emulation programs such ®...
  • Page 98: Running Without A Terminal

    Technical Reference Manual 4.2.3 Running Without a Terminal The board can boot up without a screen or terminal attached. If the speed is set to Auto and no terminal is connected, the speed is set to 115,200 bauds. Furthermore, you can run without any console at all by simply not enabling VT100 Mode and by disabling the onboard video.
  • Page 99 APPENDICES BOARD SPECIFICATIONS MEMORY & I/O MAPS INTERRUPT LINES BOARD DIAGRAMS CONNECTOR PINOUTS BIOS SETUP ERROR CODES EMERGENCY PROCEDURE GETTING HELP & RMA...
  • Page 100: Board Specifications

    Proprietary Mezzanine with PCI bus, FD and EIDE support SMBus (for power management of CPU temperature monitoring, DRAM control, clock buffers and power control) cPCI-MXS64GX: Level 1: 16/16KB instruction/Data CPU-internal Level 1 Cache Memory Level 2: 256KB internal, 64-bit wide, pipelined burst...
  • Page 101 Technical Reference Manual Board Specifications (continued) Clock/Calendar Real-time clock with (replaceable) battery backup, CMOS RAM Connectors in “Front” Front Plate configuration 15-pin D-Sub COM1 9-pin D-Sub Ethernet 1 and 2 2 x RJ-45 with built-in LEDs PS/2 mouse + Keyboard...
  • Page 102 LSI Logic Symbios ® SYM53C895 PCI to Ultra2 SCSI I/O Processor with LVD Link™ Universal Transceivers. Transfert rate up to 80MB/s Ethernet Two 10/100Mb/s Ethernet, PCI 10/100Base-TX ports (Intel 82559 controller) HD/FD Mezzanine Card Optionally onboard using Kontron’s cMC series mezzanine cards...
  • Page 103 Technical Reference Manual Board Specifications (continued) Supervisory Two-stage software programmable Watchdog timer drives NMI on 1 stage and system reset on 2 stage. Programmable CPU temperature monitor/alarm Power failure/low battery detector Front Panel LED : IDE activity and SCSI activity, Hot Swap, Ethernet and link activity MS-DOS™, Windows®...
  • Page 104 Shock Designed to meet IEC 68-2-27 Vibration Designed to meet IEC 68-2-6 Reliability MTBF: cPCI-MXS64GX : 54810 hours @ 20°C (MIL-HDBK-217F) Board serial number in EEPROM USB, keyboard and mouse protected by self-resetting fuse 2 year limited warranty Designed to meet or exceed : Safety: UL1950, CSA C22.2 No 950, EN 60950, IEC950...
  • Page 105: Memory & I/O Maps

    B. MEMORY & I/O MAPS EMORY APPING FFFFFh System BIOS E0000h 1MB to top of DRAM Optional ROM (Free) LAN BIOS if activated (~30KB) See Note 1 See Note 2 SCSI BIOS (18KB at runtime) Optional ROM (Free) C 000h Video BIOS C0000h 100000h...
  • Page 106: I/O Mapping

    Technical Reference Manual I/O M APPING Address Optional Optional Optional Function Address Address Address 000-01F DMA Controller 1 020-03F Interrupt Controller 1 040-05F Timer 060-06F Keyboard 070-07F Real-time clock 080-09F DMA Page Register 0A0-0BF Interrupt Controller 2 0C0-0DF DMA Controller 2...
  • Page 107: Interrupt Lines

    1 Available lines service on board and external PCI/ISA PnP devices or a Legacy ISA device. DMA C HANNELS The cPCI-MXS64GX integrates the functionality of two 8237 DMA controllers. Eight DMA channels are available. According to Plug and Play standards, the system BIOS automatically allocates DMA Channel 1 or 3 for the parallel port's ECP mode.
  • Page 108: Board Diagrams

    D. BOARD DIAGRAMS EVICES URFACE OUNT...
  • Page 109: Assembly Bottom Diagram

    Technical Reference Manual SSEMBLY OTTOM IAGRAM...
  • Page 110: Mounting Holes

    Board Specifications OUNTING OLES...
  • Page 111: Connector Holes

    Technical Reference Manual ONNECTOR OLES 6.849 6.299 8.971 8.734 8.459 7.759 7.159 6.494 5.191 4.636 4.084 3.892 3.669 3.659 3.374 3.309 1.909 0.000 0.000 0.059 0.216...
  • Page 112: Connector Pinouts

    E. CONNECTOR PINOUTS PCI-MXS64GX C ONNECTORS AND EADERS MXS64GX Connector J14 CPCI Bus Connector CPCI Bus Connector CPCI I/O Connector CPCI I/O Connector CPCI I/O Connector CRT VGA Connector (Front panel configuration only) Serial Port 1 – RS-232 (Front panel configuration only) Mezzanine PCI Connector Ethernet 1 Connector (Front panel configuration only) Ethernet 2 Connector (Front panel configuration only)
  • Page 113: J1 Cpci Bus

    Technical Reference Manual PCI B ROW A ROW B ROW C ROW D ROW E VCC5E -12VE +12VE VCCE VCCE INTA# INTB# INTC# VCCE INTD# RESERVED HEALTHY# VI/O INTP INTS BRSVP1A5 BRSVP1B5 RST# GNT0# REQ0# VCC3E CLK0 AD31 AD30...
  • Page 114: J2 Cpci Bus

    Connector Pinouts PCI B ROW A ROW B ROW C ROW D ROW E S_CLK1 REQ1# GNT1# REQ2# S_CLK2 S_CLK3 SYSEN# GNT2# REQ3# S_CLK4 GNT3# REQ4# GNT4# V I/O BRSV CBE7 CBE6# CBE5# V I/O CBE4# PAR64 AD63 AD62 AD61 AD60 AD59 V I/O...
  • Page 115: J3 Cpci Bus

    Technical Reference Manual PCI B ROW A ROW B ROW C ROW D ROW E SD11+ SI0+ SD9+ DIFFSENS SD10+ SCD+ SSEL+ SPEEDLED0 LINKLED_0 ACTLED0 LINKLED_1 SPEEDLED1 ACTLED_1 ETX+1_1 ETX-_1 ERX+_1 ERX-_1 WR_80# +12V +12V JDCD4# RJXD4 JDSR4 JTXD4...
  • Page 116: J4 Cpci Bus

    Connector Pinouts PCI B ROW A ROW B ROW C ROW D ROW E I2C-CLK I2C-DATA EXTFAN0FAIL EXTFAN1FAIL SM-BYPASS# SD11- SD10- SD9- SD8- SIO- SREQ- SCD- SSEL- SMSG- SRST- SACK- SBSY- SBSY+ SATN- SACK+ N.C. TERMPWR TEMPWR SDPO+ SATN+ SDP0- SD7- SD6- SD5-...
  • Page 117: J5 Cpci Bus

    Technical Reference Manual PCI B ROW A ROW B ROW C ROW D ROW E BRSTDRV# BRSTDRV# IDE0_D7 IDEO_D8 IDE0_D6 IDE0_D9 IDE0_D5 IDE0_D10 IDE0_D4 IDE0_D11 IDE0_D3 IDE0_D12 IDE0_D2 IDE0_D13 IDE0_D1 IDE0_D14 IDE0_D0 USB1_GND IDE0_D15 IRQ14 IDE0_REQ IDE0_I0RDY IDE0_IOW# IDE0_DACK#...
  • Page 118: J14, Mezzanine Pci

    Connector Pinouts J13, S 1 - RS-232 ERIAL Pin Number Pin Number Signal Flow Signal Flow Signal Top View Signal DCD 1 DSR 1 RXD 1 RTS1 TXD 1 CTS 1 DTR 1 RI 1 GND 1 J14, MEZZANINE Top View MS2_BD_SEL# PBRST# MS4_BD_SEL#...
  • Page 119: J17, Ps/2 Keyboard/Mouse

    Technical Reference Manual E.10 J15/J16, E THERNET Top View Signal Yellow Note Not Connected These two LEDs Not Connected might be reversed. Green Not Connected Not Connected E.11 J17, PS/2 K EYBOARD OUSE Front View Signal KDATA MDATA KBCLK...
  • Page 120: J19, Storage Mezzanine

    Connector Pinouts E.13 J19, S TORAGE MEZZANINE Top View PDD0 MCLK MDATA PDD1 PDD2 KBDAT KBCLK PDD3 PDD4 VCC-KBD PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 FD-DRVEN0# FD-DS1# PDD15 BRSTDRV# FD-DRVEN1# PDIOW# PDREQ FD-MTR1# FD-INDEX# FD-DS0# PIORDY0 PDIOR# FD-DSKCHG# FDET...
  • Page 121: J20, Pmc

    Technical Reference Manual E.14 J20, PMC Top View Pin Number Pin Number Signal Top View Signal Not Connected -12V INTA# INTB# INTC# BUSMODE1# INTD# Not Connected Not Connected PCLK GNT # REQ –# AD31 AD28 AD27 AD25 C/BE3# AD22...
  • Page 122: J21, Pmc

    Connector Pinouts E.15 J21, PMC Top View Pin Number Pin Number Signal Top View Signal +12V Not Connected Not Connected Not Connected Not Connected Not Connected Not Connected Not Connected BUSMODE2# VCC3 PCIRST# BUSMODE3# VCC3 BUSMODE4# Not Connected AD30 AD29 AD26 AD24 VCC3...
  • Page 123: Hot Swap Switch

    Technical Reference Manual E.16 H WITCH Signal Top View VCC3E SW_OPEN# E.17 S1 – R ESET WITCH Signal View RESET# E.18 BT1, CMOS B ATTERY ACKUP ONNECTOR Signal Front View Battery (+) Battery (-) E-12...
  • Page 124: Bios Setup Error Codes

    F. BIOS SETUP ERROR CODES POST B POST beep codes are defined in the BIOS to provide low level tone indication when an error occurs during the BIOS initialization. Beep codes consist of a combination of long and short beeps. They are described as follows: Beep Codes Post code...
  • Page 125: Error Messages

    If it’s the first boot, check for the onboard battery jumper (jumper W4 for both the cPCI-MXS64GX). The board is shipped with W4 jumper set to OFF (onboard battery disconnected). This jumper must be shorted (ON) for proper battery operation.
  • Page 126: Post Codes

    POST access correct. If not, show POST FE and beep continuously… Autodetect Flash EPROM. Test CMOS Interface and Install the Kontron segment. Battery Status Verifies CMOS is working correctly (walking bit test). Restore CMOS from Flash if option is enabled.
  • Page 127 Technical Reference Manual POST Codes (continued) POST # Designation Description Initialize Keyboard Open Xilinx I/O Port Boot Block 1 : Verify BIOS location to x90h (X=1,2 or checksum. 3) inside the chipset (if necessary). Disable (if necessary). Boot Block in EMERGENCY 2 Thermal Management.
  • Page 128 BIOS Setup Error Codes POST Codes (continued) POST # Designation Description Test Struck 8259's Interrupt Bits Nothing Test 8259 Interrupt functionality Force an interrupt and verify that the interrupt occurred (IRQ 0 - clock int. 8h). Test Struck NMI Bits (Parity/ IO Nothing.
  • Page 129 Install the Kontron segment from 7000:0h to EC00:0h. Check & Program CPLD Check & Program CPLD for valid UserCode & IDCode. Kontron CRC Check Check if Kontron block have a valid CRC. If not, the Emergency procedure is launched. 85-AF Reserved...
  • Page 130 BIOS Setup Error Codes POST Codes (continued) POST # Designation Description Very Early Initialization OEM Specific – Initialize hardware before any other hardware initialization. CB-CF Reserved Reserved Power Management Full speed Trying to go back or into full speed mode. Power Management -- Doze Trying to go or in Doze mode.
  • Page 131: Emergency Procedure

    G. EMERGENCY PROCEDURE Follow this procedure only in case of emergency such as a critical error occurred during the Boot Block Flash BIOS update (when using UBIOS utility program or if you meet one of the following symptoms at anytime: No POST code on a power up (when using a POST card).
  • Page 132: Generate An Emergency Floppy Diskette

    LOPPY ISKETTE Use a system that has a 1.44 Mbytes floppy drive A. Insert the Kontron Emergency Diskette in drive A: Copy the two files WDISK.COM and EMERDISK.TEK to your hard drive (those files are available from the driver’s CDROM).
  • Page 133: Getting Help

    Tel. (800) 354-4223 Fax: (450) 437-8053 Internet : www.Kontron.com E-Mail : support@kontron.com If you have any questions about Kontron, our products or services, you may reach us at the above numbers or by writing to : Kontron Communications, Inc. 616 Curé Boivin Boisbriand, Québec...
  • Page 134 Technical Reference Manual Returning Defective Merchandise If your Kontron product malfunctions, please do the following before returning any merchandise: 1) Call our Technical Support department in Canada at (450) 437-5682. Make certain you have the following at hand: •...
  • Page 135 : ___________________ Postal/Zip Code: _______________ Phone Number : ___________________ Extension : ___________________ Fax Number : __________________ P.O. # Serial Number Failure or Problem Description (if not under warranty) Fax this form to Kontron’s Technical Support department in Canada at (450) 437-8053...

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