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Intel® Server System M50FCP1UR System Integration and Service Guide
Error Code
Recovery boot has been initiated.
Note: The Primary BIOS image may be corrupted or the
8607
system may hang during POST. A BIOS update is
required.
A100
BIOS ACM Error
A421
PCI component encountered a SERR error
A5A0
PCI Express component encountered a PERR error
A5A1
PCI Express component encountered an SERR error
DXE Boot Services driver: Not enough memory available
A6A0
to shadow a Legacy Option ROM.
E.1
POST Error Beep Codes
The following table lists the POST error beep codes. Before system video initialization, the BIOS uses these
beep codes to inform users on error conditions. The beep code is followed by a user-visible code on the
POST progress LEDs.
Beeps
Error Message
3 short
Memory error
3 long
and 1
CPU mismatch error
short
The integrated BMC may generate beep codes upon detection of failure conditions. Beep codes are sounded
each time that the problem is discovered, such as on each power-up attempt, but are not sounded
continuously. Codes that are common across all Intel server boards and systems that use same generation
chipset are listed in the following table. Each digit in the code is represented by a sequence of beeps whose
count is equal to the digit.
Code
1-5-1-2
VR Watchdog Timer sensor assertion.
A PSU reports a failure, or the BMC detects the presence of a PSU
1-5-1-4
model that is incompatible with one or more other PSUs in the
system.
1-5-2-1
No CPUs installed or the first CPU socket is empty.
1-5-2-2
CPU CAT Error (IERR) assertion.
1-5-2-3
CPU ERR2 timeout assertion.
1-5-2-4
CPU/VR mismatch.
1-5-2-5
CPU population error.
1-5-4-2
Power fault: DC power is unexpectedly lost (power good dropout).
1-5-4-4
Power control fault (power good assertion timeout).
Error Message
Table 13. POST Error Beep Codes
POST Progress Code
Multiple
E5, E6
Table 14. Integrated BMC Beep Codes
Reason for Beep
Action Message
Disable option ROM at SETUP to save
runtime memory.
System halted because a fatal error related to the memory was
detected.
System halted because a fatal error related to the CPU
family/core/cache mismatch was detected.
VR Watchdog Timer.
PS Status.
CPU Missing sensor.
CPU Status sensor.
CPU ERR2 Timeout sensor.
CPU Status sensor (configuration error
offset).
CPU 0 Status sensor.
Power Unit – Power unit failure offset.
Power Unit – Soft power control failure
offset.
Description
Associated Sensors
Type
Fatal
Major
Fatal
Minor
Fatal
Minor
111
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