Ucf Location Constraints - Xilinx Spartan-3E User Manual

Chapter 10: Analog Capture Circuit
SPI_MISO
AD_CONV
Spartan-3E
Z
FPGA
SPI_SCK
Master
Sample
point
AD_CONV
SPI_SCK
SPI_MISO
Figure 10-7
SPI slave select enable. Be sure to provide enough SPI_SCK clock cycles so that the ADC
leaves the SPI_MISO signal in the high-impedance state. Otherwise, the ADC blocks
communication to the other SPI peripherals. As shown in
communications sequence. The ADC 3-states its data output for two clock cycles before
and after each 14-bit data transfer.
4ns min
AD_CONV
3ns
SPI_SCK
SPI_MISO
AD_CONV

UCF Location Constraints

Figure 10-8
including the I/O pin assignment and I/O standard used.
78
D D D D D D D D D
0 1 2 3 4 5 6 7 8
Channel 1
Converted data is presented with a latency of one sample.
The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV.
The converted values is then presented after the next AD_CONV pulse.
Channel 0
13
Figure 10-6: Analog-to-Digital Conversion Interface
shows detailed transaction timing. The AD_CONV signal is not a traditional
1 2 3
High-Z
30
SPI_SCK
Channel 1
3 2
SPI_MISO
The A/D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cycles
Figure 10-7: Detailed SPI Timing to ADC
provides the User Constraint File (UCF) constraints for the amplifier interface,
NET "AD_CONV" LOC = "P11" |
NET "SPI_SCK" LOC = "U16" |
NET "SPI_MISO" LOC = "N10" |
Figure 10-8: UCF Location Constraints for the ADC Interface
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Slave: LTC1407A-1 A/D Converter
D D D D D D D D D
9 10 11 12 13 0 1 2
Z
Channel 1
13
0
19.6ns min
4
5
8ns
Channel 0
13 12
31 32 33
1 0
IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 ;
Spartan-3E Starter Kit Board User Guide
D D D D D D D D D
3 4 5 6 7 8 9 10 11 12
Channel 0
Sample
point
0
UG230_c10_05_030306
Figure 10-6, use a 34-cycle
6
11
45ns min
34
6ns
High-Z
UG230_c10_06_022306
SLEW = SLOW | DRIVE
SLEW = SLOW | DRIVE
UG230 (v1.0) March 9, 2006
R
D
13
Z
Channel 0
13
= 6 ;
= 8 ;