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Chapter 5: Character LCD Screen
Character LCD Interface Signals
Table 5-1
Table 5-1: Character LCD Interface
Voltage Compatibility
The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V.
However, the FPGA's output levels are recognized as valid Low or High logic levels by the
LCD. The LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs
provided by the FPGA meet the 5V TTL voltage level requirements.
The 390Ω series resistors on the data lines prevent overstressing on the FPGA and
StrataFlash I/O pins when the character LCD drives a High logic value. The character LCD
drives the data lines when LCD_RW is High. Most applications treat the LCD as a write-
only peripheral and never read from from the display.
Interaction with Intel StrataFlash
As shown in
lines SF_D<11:8>. As shown in
application usage in the design. When the StrataFlash memory is disabled (SF_CE0 =
High), then the FPGA application has full read/write access to the LCD. Conversely, when
LCD read operations are disabled (LCD_RW = Low), then the FPGA application has full
read/write access to the StrataFlash memory
Table 5-2: LCD/StrataFlash Control Interaction
Notes:
1. 'X' indicates a don't care, can be either 0 or 1.
42
shows the interface character LCD interface signals.
Signal Name
FPGA Pin
SF_D<11>
M15
SF_D<10>
P17
SF_D<9>
R16
SF_D<8>
R15
LCD_E
M18
LCD_RS
L18
LCD_RW
L17
Figure
5-1, the four LCD data signals are also shared with StrataFlash data
SF_CE0
SF_BYTE LCD_RW
1
X
X
X
X
0
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Data bit DB7
Data bit DB6
Data bit DB5
Data bit DB4
Read/Write Enable Pulse
0: Disabled
1: Read/Write operation enabled
Register Select
0: Instruction register during write operations. Busy
Flash during read operations
1: Data for read or write operations
Read/Write Control
0: WRITE, LCD accepts data
1: READ, LCD presents data
Table
5-2, the LCD/StrataFlash interaction depends on the
X
StrataFlash disabled. Full read/write access to LCD.
0
LCD write access only. Full access to StrataFlash.
StrataFlash in byte-wide (x8) mode. Upper data lines
X
are not used. Full access to both LCD and StrataFlash.
Spartan-3E Starter Kit Board User Guide
Function
Shared with StrataFlash pins
SF_D<11:8>
Operation
UG230 (v1.0) March 9, 2006
R
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